8257 DMA Controller

Want notes and block diagram of 8257 DMA Controller.

fabrication of IC

what is fabrication? what are the various fabrication techniques?

power amplifiers

why do power amplifiers need large amplitude signal at its output.why do we get get noise when we send small scale amplitude signals. what is the function of baseband amplifiers

Regarding Area constraint in the Device

am having 8-bitALU component resource. Can any one tell me how will i get the number, which is how many number of 8-bitALU'S can fit into the particular xilinx Device(xc4vfx60-11-ff1152

VHDL code for 8-bit DES(Data Encryption Std)

Want VHDL code for 8-bit DES(Data Encryption Standard)...

VHDL CODING OF UART

PLEASE GIVE ME VHDL CODE OF UART

Multiplier Code in Verilog

can anyone tell me how to write a code for a multiplier with two 16 bit inputs?

Cyclone III and Spansion SPI Flash

I am using Cyclone III FPGA in my project for configuration of FPGA i wanted to use Spansion SPI flash in place of EPCS but i found that there are some errors may occur while programing SPI flash with Quartus II. Can anyone suggest me the way to avoid the issues in programming spansion SPI flash connected to cyclone III.

delay in vhdl

i am designing a traffic light controller in vhdl.i want to know how to give delay to change over the signal in finite state machine program with a inbuilt clock of 24MHZ.can somebody help me to finish my design?

Design and simulation of circuits

1. How can i design and simulate a circuit to count the number of 1s in a 7-bit input word and return it in a 3-bit output word. a) Use verilog structural modelling and 1-bit full-adders as the building block of your cct. How many Logic elements(LE) are needed to implement your design in the Cyclone II FPGA device (EP2C70F672C7)? How many FAs are needed? b) How many Full- Adders would be needed if the input word was 15-bit wide?

4 bit memory

can anyy one have a idea on 4 bit memory,,, i have to design this for a pressure sensor in pspice,,,

cricuit methods to solve signal integrity problems

I wanted to know what are the different circuit methods (not fabrication methods) available to solve the signal integrity problems in deepsubmicron technologies.

a bridge between apb and i2cslave?

need the bridge description of apb master to i2c slave apb works at 6 mhz and send 32 bits parallel data i2c works at 3mhz and receives the 8 bit serial data what wil be the decoder logic between bridge and i2c interface"? bridge wil work at wat frequency? i chosen bridge as asynchronous dual port fifo?
Detail pl.

CMOS Camera interface Question.

First let me start off by saying I hope I posted this question in the right place. Now my real question. I have just been getting into the world of robotics and so far it has been going great. I only have one problem; I purchased a CMOS camera but I cant use it because it uses a parallel output. I want to make a small board to convert the parallel output to a serial output but I am not sure how. The camera uses a 8 bit parallel connection and it has been suggested to me that I should use a 8 bit PAR/SER shift register but I am looking for a second opinion so I know for certain what I should do.

IAR embedded workbench sensor code

I have to do code for a low power sensor system. It is a MSP430 based resistance sensor measurement system that has 3 variable sleep times depening on the resistance been measured
help me please with the code ?

: BZ-FAD

need vhdl code for BZ-FAD architecture.......or hot block ring counter dat was used in it...

Depth to Address width in verilog

I am reading this topic "verilog code for RAM and FIFO" in which address width of the address bus is given as - parameter ADDR_BUS_WD = 1>>DEPTH; //Address bus width My question is, why is this supposed to work? The reason I ask is because it is not working for me in Aldec's Riviera Pro tool.

Need ADC for DAQ system

am making a PC controlled data acquisition system in which i've used ADC0808 whose conversion time is 100microseconds. I want to replace it by another one having less conversion time.

Verilog code for RAM

(1) I am trying to design a 128bytes RAM similar to tht of 8051 using verilog... plz

clock division

need code for clock division in VHDL

importance of delays

What is the importance of delays in digital circuits(combinational and sequential),and what we actually mean by recovery and removal times? what is the consequence if these conditions (recovery and removal times)are not met for a circuit?

16 bit multi-operand Comparator

send me or guide for a synthesizable vhdl code for a 16 bit multi-operand comparator.

Industrial Application of 8085 microprocessor

I want an application of the 8085 in detail with the block diagram and description of the application.

What is better FPGA or CPLD?

which 1 is betterfpga or cpld and why? and, why there grade speeds r mentioned as negative values?

i need a verilog code for braille code

i need a program/code for braille code..

shift multiplier

i want to know the ASM chart and verilog HDL code for 4bit shift multiplier... can anybody help me..

coding for electronic digital clock

i want to know the vhdl and c lang. coding for digital clock based on PIC16F84A micro controller?

ETHERNET/IP

I want to modify the ethernet (10/100) ip core to industrial ip core. so any one pl give me detail about industrial ip core and its specification...?

VHDL and FPGA

want a Project idea for Real time implementation to do in VHDL...

analog integrated circuits

can anyone pls explain me wats the exact need for going to analog integrated circuits? Advantage of analog integrated circuit over the digital one?

sl 100

i want to know about sl 100, it's working and application in circuit.

Phase Shift

Can anyone pl explain me how is there no phase shift in oscillator but there in amplifier.....also significance of phase shift

edge trigger Master slave

I want to konw if +ve edge triggering possible in master slave and also Is edge triggerin possible in JK flip flop

4-bit counter code in VHDL.

Have to do a 4-bit counter code in VHDL. It hads a 4 line input (A) a 10Hz CLK input a load input which is asynchronous a UP/Down (Down is Not down) and is synchronous a Reset input which is asynchronous a 2 line setect input line (x) a 2 line setect input line (y) a 4 line output (count) a one line output called (xeq Y) Does anyone know the code

dumping the vhdl code into 2 vertex II-pro kits

I am using two vertex II pro kits.I need to dump some modules into one fpga and some other into another fpga,can you tell me how to dump the code into two fpgas.

VHDL-AMS - hAMSter

I am working in hAMSter, A VHDL AMS tool. I would like to know , whether I will be able to represent a random signal, whose data I have, as a SIGNAL to be processed in a hAMSter program. The hAMSter program is developed and it is working, only thing is I should send my random data from a dat file in to the hAMSter program by some file I/o process as a "SIGNAL" or some entity. Is it possible.

Reading Files in Verilog

Can anyone help me like how it should be done? I need to Read R G B values of each pixel from 3 separate file and Write the corresponding Y U V files separately.

Solutions of Rabaey

I need solutions to Digital Integrated Ckts, Jan rabey.

counter frequency vhdl code.

need the code for counter frequency coding in vhdl.

E123 MUX / DEMUX Transceiver IP Core

please frd me to verilog code( which can be synthesized ) or block diagram or any details regarding the below mentioned.
The E123MUX is a VLSI core that provides the E13 functions needed to multiplex and demultiplex 16 independent E1 signals to and from an E3 signal that conforms to the ITU-T G.751 Recommendation. The E1 and E3 signal an interface is NRZ only. The E123MUX can also be configured to operate as an E12 or E23 multiplexer and demultiplexer. Sixteen E1 signals can be multiplexed and demultiplexed to and from four E2 signals that conform to the ITU-T G.742 Recommendation. Alternatively, four E2 signals can be multiplexed and demultiplexed to and from one E3 signal. The E2 signal interfaces are also NRZ only. Any 4 lines of 16 E1s can be multiplexed in one E2.The E123MUX uses memory locations for setting control bits and reporting status information. Microprocessor 8-bit bus provides the access of memory locations of E123MUX/DEMUX.
Feature Summary: E1 (2048 kbit/s) multiplexer/demultiplexer for ITU-T Recommendations: G.742 (8448 kbit/s E2 frame format) G.751 (34368 kbit/s E3 frame format) Multiplexer/demultiplexer converts: 16 E1s to/from 1 E3 (E13 skip mux), or 16 E1s to/from 4 E2s, or 4 E2s to/from 1 E3 (E12/E23 split mux) Select any 4 E1s to make one E2 through microprocessor interface Generates and detects E2 and E3 alarms Microprocessor input/output 8-bit bus provides split mode Intel interface

Use clock skew to increase sys. freq?

Is it possible to use clock skew (negative/positive) to actually increase the performance of the system, rather than simply having zero clock skew?

cmos comparator

want to design comparator using a charge-storage amplifier which fabricated using a 0.8μm standard logic CMOS technology,pl. give me spice model parameters.

verilog code for 5 bit sequence detector

Wanted verilog code for the sequence 11010

how to gve delay to rotate stepper motor

..plz can any body suggest me to how modify it work succesfully entity step3 is Port (clk : in STD_LOGIC; dout : out STD_LOGIC_VECTOR (3 downto 0)); end step3; architecture Behavioral of step3 is signal count:std_logic_vector(15 downto 0):=x"0000"; constant dl:time:=3 ms; begin process(clk) begin if(rising_edge(clk))then count<=count+1; dout<="1010"after dl; dout<="1001"after dl; dout<="0101"after dl; dout<="0110"after dl; if(count>x"B71B0")then count<=x"0000"; end if; end if; end process; end Behavioral;

SOC verification

have a simple SOC which contains processor , DMA and some IP peripherals. Could you please tell me how the verification flow(trigger IP)in soc level.

distance between drain and source of cmos

why do not we reduce the distance between drain and source of a cmos transistor while in the stage of fabrication it self for better multimedia appilications??? is there any limitations

vhdl code for shift register 7495

What is vhdl code for 4 bit counter 7493,shift register 7495..

vertexII

vertexII is not available,if i will implement in spartan3 is there any major diff. in the result

can we use signal in case statement

can we use signal in case statenment ,if yes how it would be synthesized..

IC 7495

please any one let me know the operation and vhdl code for ic 7495 (universal shift register)?

procedure sttements

Let me know how 2 use procedure statements with simple example?

vertexII

leonardo spectrum download

can anyone tell me from where i can download leonardo spectrum???

CODIFICADOR QPSK

needed vhdlcode for condificador qpsk

program relocation

plz send me complete notes on the PROGRAM RELOCATION FOR INTEL 8086 MICROPROCESSOR.

CMOS over BJT's

What are the advantages of using CMOS instead 0f BJTs for realizing digital circuits?

Blocking & Non Blocking

when I code Flip-Flop or Shift Registers. The data latches on the flip-flop on the next edge of the clock but not on the desired clock edge . Why does this happen . I even tried different combinations with blocking and non-blocking statements "= ,<=" The results are the same .

how to determine gate length from technology file

My question is how to determine the gate length from the interconnect technology file (ITF). For ex. the technology file I have is CONDUCTOR IPOLY_FINAL { THICKNESS=0.070 WMIN=0.045 SMIN=0.115 RPSQ=10.0 CRT1=0.0027 } From this how do you know the gate length and which process node it is.

verilog hdl

verilog hdl codes for 4-bitadders,subtractors,counters,JK-flipflop,T-flipflop

Why Microprocessor is called so

Why microprocessor is called microprocessor & why not only processor ?

VHDL FOR ADC?

CAN ANYONE HELP ME SENDING THE VHDL CODE FOR ADC0809 FPGA INTERFACE

adder

how many multiplexers are required to design a full adder

polymer

1) i wish to know that Polyphinylene vinylene is optically transperant or not? 2)solvents that can dissole PPV

verilog code 4 low power shift-and-add multiplier

needed verilog code 4 low power shift-and-add multiplier

Certifications in VLSI stream

let me know what are the certifications available for a VLSI engineer either in digital or analog stream?

RS Decoder

Can anyone send me the VHDL code for Reed Solomon Decoder(15,11).

sine wave o/p of given frequency using DAC

want to generate the sine wave of certain frequency using DAC,verilog code too needed

opcodes

needed complete opcode list for intel 8086 microprocessor.. can anyone help me out please..?

4bit risc processor

need code for 4bit risc processor

BLUE EYES TECH.

WANT TO GIVE A PRESENTATION ON BLUE EYES TECHNOLOGY. PLEASE SEND ALL INFORMATION ABOUT IT...

Active Devices

What is Active device?explain, is transistor active device or not?

logic family

Lowest noise margin in which logic family is?? a) TTL b) CMOS c) biCMOS d) all have same

how to use rocketIO in vertex-5 to invert serial t

I need to use Rocket IO(GTX) in vertex 5 to convert high speed serial data to parallel. I read ug198,ug024,ug204 of xilinx, i just want a simple code and simulation that shows serial data come and change to parallel.

8-bit sine-wave generator at 10 KHz VHDL

Can anyone show me the complete source code of VHDL of an 8-bit sine-wave generator at 10 KHz?

verilog programs

i need verilog programs for 3 modeling

Verilog code for 8251 USART circuit

Does someone have an either behavioral, or structural description of the 8251 USART circuit in Verilog? I need it for a university-project.

sea

want vhdl code for scalable encryption algorithm

increase in pattern count while ATPG DFT

Can anyone suggest on my ques? 1) I had a netlist I generated pattern say 1000 count ,later I had next version of same netlist but if you see the ET generates 11000 patterns. Can anyone update the reason for increase in teh vector count? only-2 scan clocks 2-scan reset. 1st release say 10000 flops 2nd release say 10050 flops.

increase in pattern count while ATPG

Can anyone suggest on my ques? 1) I had a netlist I generated pattern say 1000 count ,later I had next version of same netlist but if you see the ET generates 11000 patterns. Can anyone update the reason for increase in teh vector count? only-2 scan clocks 2-scan reset. 1st release say 10000 flops 2nd release say 10050 flops.

drawing stick diagram

want to know the basics for drawing stick diagram

solutions for Antenna Theory

Could I get the solutions for Antenna Theory and Design (2nd Ed., Stutzman & Thiele)Please?

How to get into the field of research?

Someone pl, guide me through the process for getting into the field of research in digital electronics.

microwind

i need to know abt MICROWIND software.anyone who knows the same,please help me...

define a matrix in verilog

i want to implement duetcsh jozsa problem of quantum mechanics on fpga so i want to know how we can define a matrix in verilog and how can i multiply two matrix in verilog

electronic voting machine

i am trying to implement an Electronic Voting Machine in vlsi. can anyone plz give me an idea how to start with it or suggest some website where they can give me details about the same. i want my result(no. of votes gained by each candidate) to be displayed on 7 segment of my FPGA board. so can anyone highlight me how to write the code for the same.

prpgram

i want solution for following
program to simulate tossing of die using vector interrupt key and rst7.5
program to add two 8-bit BCD number without using DAA instruction

program

Iwant program
1.8085 program to add two 8 bit data without using accumulator register.
2.To find (n^2)^2 - n is a hexa decimal number

program

I want fibonacii series program with algorithm

www.asic.co.in

I found this new site www.asic.co.in it contains real time interview questions(FPGA, RTL, CMOS,SYNTHESIS) compiled from many design engineer interview experience a must see and read for every VLSI engineer.

report on blue eyes

plz let me know the report on blue eyes

information of microcontroller

how can I started with microcontroller?

basic of microcontroller

i want know about the microcontroller (89c51) basics and its applications.and also its basic troubles when we connect it into the circuit.

many inputs to fpga kit

am working with spartan 3 AN kit.in my project i have 58 inputs. i dont know how to assign this 58 pin in my fpga kit.can i pass my inputs in any other way.

static and dynamic resistance

please explain me about dynamic resistance and static resistance

verilog code for digital calculator

vlsi paper prestation

i like to do paper prestation on vlsi, can u suggest any site to get any old paper. so that i get some idea about that.

use PTM model in hspice

want to use ptm 90nm bulk cmos in hspice, but it has an error "syntax of .lib can not be realized" , help me please.

code for 32 bit floating point ALU

pl. send me the vhdl code for 32 bit floating point ALU(adder,subtractor,multiplier and divider) that follows IEEE754 standard.

LCD interfacing with CPLD

We have VHDL code for LCD display on SPARTAN-3 Kit. Still, we have a probleam of LCD interfacing with CPLD. d

thesis

i m persuing mtech(vlsi) from manit bhopal can anybody suggest me topic for thesis

Wallace tree 32-bit Multiplier VHDL code

I work on my thesis and I want to simulate my theories, but I can not write VHDL code very well. please help on my problem.

verilog code for USB 2.0

need verilog code for protocol of USB 2.0

CMOS

why subthreshold current is there in CMsubOS???

floating point alu in vhdl ineed uagently

....iam doing my project on floating point alu in vhdl...secure arithmetic coding in vhdl...plz send me floating point add,sub,mul i need..

i need floating pt alu

.plz send me floating pt alu vhdl code.

floating point division+vhdl code

iwant vhdl code for floating point division.help me

netbook and vlsi applications

is it possible to run vlsi/fpga/embedded tools/applications in netbook? what about performance,speed on running these programs?

digital energy meter

i need a complete project thesis, hardwarre and software on digital energy meter. any body help me in this regard. thanks

I NEED A MOBILE CIRCUIT DIAGRAMS

ANY HAVE A COMPLETE DIAGRAMS SEEND TO ME PLEASE

verilog code 4 4-bit alu

can anyone give me a 4-bit alu verilog code?

parallel in serial out

please give the parellel in serial out verilog program.

setup and hold tim

Why is the set up and hold time required at all....i mean where is this extratime helped in the circuit..can u explain w.r.t to the cmos structure of the Flip Flop...as in is that some cap requires that or something else which requires that

mobile circuit diagram

I need all type of nokia mobile circiut diagram.

vt of nmos

gate is responsible for the formation of channel.if the gate voltage is greater than vt then channel will form.then why the reason for getting VDD-Vt rather than VDD at the source,as VDD is not responsible for formation of channel.

: 8 point FFT in FPGA

if any body has the code for 8 point FFT for XILINX spartan board

Simulation Types

What are the different types of simulation like functional simulation, timing simulation , ...

8-bit square root

i need to implemant an 8-bit square root code

fpga based alarm door security

i need to design an alarm door security by using vhdl that will embedded on fpga.this security will use keypad that need user to enter the password for security. if the user enter the wrong password for three times,this alarm will be ringing instead of block the door. please help me in designing the source code for programming the ic by using vhdl.

many inputs to fpga kit

i am working with spartan 3 AN kit.in my project i have 58 inputs. i dont know how to assign this 58 pin in my fpga kit.can i pass my inputs in any other way.

fast bus serial or parallel

I'm looking for a way to connect my peripheral chip with main application processors or base band chips (external connection i.e. on board). I don't want to use PHY for serial interconnect. For example, currently I’m using SPI which is fast enough (40 MHz) but I want to be compatible with other fast I/Fs. what protocols do you know that are used by main AP vendors? TI, Broadcom, Qualcom, Samsung, Marvel, etc?

details about clock cycles

kindly explain me about the number of clock cycles needed for division in 8086 processor.

evolution modes of 8085 microprocessor

what are evolution modes and addressing modes of microprocessor

adder

how many multiplexers are required to design a full adder

8 point FFT in FPGA

if any body has the code for 8 point FFT for XILINX spartan board ,please help

declaring an integer in port map

how do i declare an integer using port map? I wish to connect the address lines of my rom module to the address controlling lines of my other module how do i go about this? for example i have an address which is integer range 0 to 5. Is this the proper way to write it?
U1: cntrl_module port map (adress(0)

how to write the code of image in verilog

dont known how to write the code of 512*512 grayscale image in verilog.

Ring Oscillator

have few questions abt RO, I know how it works but: what is it used for, i read that it is used for measuring delay. but delay of what? and how? Please clarify my question.

Keep_hierarchy

What is keep hierarchy in xilinx xst for what purpose it is used?

topics regarding project

i am pursuing m.tech in VLSI and i need a good VLSI project that is based on communication , it can be based on any software but i would prefer CADENCE tool as it is available at my institute. so plz anyone, help me out if you have a solution to my problem.

trafic light conversion

I am trying to convert an old bulb style traffic light to work on house current! 120 volt. Can someone help me?

hardware accelerator detection in xilinx microblaz

similar to impulseC in xilinx-microblaze is there any solution to automatically detect which portions to be converted to hardware accelerator for optimization?

WARNING:Xst:647 - Input is never used.

i dont understand why it showing the particular error; answer with reason? entity rising_edgefuntion is port (clk : in std_logic; a : in std_logic; b : out std_logic); function sathish_falling_edge(signal s: std_logic) return boolean is begin if (s'event) and (s = '0') and (s'last_value= '1') then return true; else return false; end if; end sathish_falling_edge; end rising_edgefuntion; architecture Behavioral of rising_edgefuntion is begin process(clk,a) begin if sathish_falling_edge(clk) then b <= a; end if; end process; end Behavioral;

akhilnair

want ans about internal architecture of 8085

microblaze project

pl suggest a project idea using virtex5 microblaze as part of m.tech(vlsi&es)

why IDDQ and IDDT

can any one tell about iddq and iddt testing

E123 MUX / DEMUX Transceiver IP Core

please frd me to verilog code( which can be synthesized ) or block diagram or any details regarding the below mentioned. The E123MUX is a VLSI core that provides the E13 functions needed to multiplex and demultiplex 16 independent E1 signals to and from an E3 signal that conforms to the ITU-T G.751 Recommendation. The E1 and E3 signal an interface is NRZ only. The E123MUX can also be configured to operate as an E12 or E23 multiplexer and demultiplexer. Sixteen E1 signals can be multiplexed and demultiplexed to and from four E2 signals that conform to the ITU-T G.742 Recommendation. Alternatively, four E2 signals can be multiplexed and demultiplexed to and from one E3 signal. The E2 signal interfaces are also NRZ only. Any 4 lines of 16 E1s can be multiplexed in one E2.The E123MUX uses memory locations for setting control bits and reporting status information. Microprocessor 8-bit bus provides the access of memory locations of E123MUX/DEMUX. Feature Summary: E1 (2048 kbit/s) multiplexer/demultiplexer for ITU-T Recommendations: G.742 (8448 kbit/s E2 frame format) G.751 (34368 kbit/s E3 frame format) Multiplexer/demultiplexer converts: 16 E1s to/from 1 E3 (E13 skip mux), or 16 E1s to/from 4 E2s, or 4 E2s to/from 1 E3 (E12/E23 split mux) Select any 4 E1s to make one E2 through microprocessor interface Generates and detects E2 and E3 alarms Microprocessor input/output 8-bit bus provides split mode Intel interface

dynamics solutions

i am interested in finding the solutions in the 11th edition hibbeler ,in chapter 13 in dynamics

80286, 80386, 80486 Architecture and Pin conf

I just need a complete notes on 80286, 80386, 80486 Architecture and Pin configuration notes.

8086 interfacing with 8237/57

please give me detailed info of 8086 interfacing with 8237/57

4 bit multiplier with shift and add

Can anyone send me a 4 bit multiplier with shift and add method within 12 hour? please...

5 bit sequence detector

i need a vhdl code for 5 bit sequence detector

microprocessor 80286

provide me with a complete informations about 80286 architecture and pin configuration

RTC DS1307 INTERFACING IN VHDL

I AM DESIGNING A DAQ PROJECT. FOR THIS I NEED THE IDEA FOR RTC INTERFACING WITH FPGA IN VHDL? CAN ANYONE SEND ME THE SUGGESTION ?

what is FPGA & ASIC?

i know the functionality of PAL,PLA. but i could't understand the logic blocks of cpld & fpga. Give some details & web address for the same. which book i have to follow? i have some doubts. 1.Is FPGA only for digital ckts? For analog circuit design what we r using? 2.What r the other technologies(like FPGA & ASIC)existing for IC Design(digital & Analog)? 3.What is EDA tools? 4.i need some details that hardware design Engineer must know.

vhdl code for solar tracker

please send vhdl code for solar tracker

size NMOS and PMOS to increase Vt

How do you size NMOS and PMOS transistors to increase the threshold voltage ?

vlsi tecnology

1what is the main difference between fpga and asic 2while simulating the cell in vlsi by using cad tools for vlsi which language is used is it same as vhdl 3 how vhdl and vlsi are interrelated 4 what is the difference between fullcustom and semicustom design

exponential function code in vhdl

want urgently.please explain code in vhdl/verilog

need code for division in 8086

please send me code for 64 by 32 bit diviion in 8086 microprocessor

difference between microprocessor and microcon

please explain in detail the difference between microprocessor and microconroller

Stepper motor datasheet

any one have the datasheets of stepper motor than pls

what is a "timing arc"?

don't know what it is "timing arc" in VLSI. I saw a article. it mentioned a FF has one timing arc. A LATCH has two timing arc. would you explain about "timing arc"?

Cryptography and Network

Please provide the solution manual to Cryptography and Network Security

programs related to logical design

i need all programs related to logical design in verilog

FAN IN & FAN OUT

.i am really cofused with these two words FAN IN & FAN OUT.can anyone explain me these two?

Dalgorthem

iam doing project on D-algorthem,pls help to develop the vhdl code

Need to reconfigure FPGA on NIOS developement kit

Iam having NIOS developement kit Startix edition. When i put on the power supply it goes to preconfigured bit stream is activated.Even after removing flash and eventhough we program the new sof in FPGA.Due to this the LEDs are continuously glowing.could you help me how to burn a standalone RTL on to this board(FPGA)..

Floating Point ALU

how can i generate code for floating point ALU (adder,subtractor & multiplier) in VERILOG? and also give the idea of synthesis report of it.

tell me adout Analog VLSI

help me in understanding Analog VLSI (with the help of example) plzzz give me any EXAMPLE project on it

VHDL Code for floating point multiplication

need VHDL benchmark program of floating point multiplication

microprocessor design

how can i design a microprocessor system using a single memory space for both ROM and RAM and INPUT/OUTPUT ports noting the limitation on the number of input and output ports on 8085A microprocessor reference

ebooks download on vlsi

i want the website for ebooks download on vlsi.plz

crc implementation

1.1 Read the data frame sequence length from the user in a named file (frame is sequence of bits variable from a minimum size to maximum size). The program should read: 1.1.1 the file of pattern of 0 and 1 and 1.1.2 its max. length defined by the length and be stored in file.

need a simple code

can somebody plz give me a code in verilog that converts a 12 bit binary number into a decimal number.

Speed checker for highways

I've a speed checker circuit which is based on timer IC.This circuit mainly consists of two LDR and two leser and seven segment display for showing the counting.That counting will give the speed/hr by using a formula i.e speed=3600/counting.Now my question is ,how can i convert that counting into visual unit.Means that speed should be display by using 7-segment.

8086 microprocessor & assembly language

i need full notes on 8086 microprocessor &assemply language programming.

artificial passenget

want to give a ppt on artificial passenger .please help me.

verilog code of DES encryption

i am in urgent need of DES code in verilog. have made the code but i am not able to do the timing analysis .

alp pgms

get me ans for 1)alp for ascending using 8085 2)architecture &block diagram of keyboard dislay interfacing with 8085 3)alp for largest in array using 8085

Biasing Circuit in CMOS

how to implement biasing circuit in CMOS. Does it's structure depends on opamp circuit? Pls explain to me what is the criteria for designing the biasing circuit?

Registring layout design

how can we compare two Integrated circuits layout to stop piracy of layout?

some problems plz help!

my queries! 1.how can we get a 3/2 clock,ie a clock output with high for 1 and a half cycle of input clock and low for one clock cycle of input? 2.why do constant current source made from BJT have high gain? 3.why is offset voltage present in saturated BJT and not in MOSFET? 4.how does putting a source follower as output stage in opamp help in avoiding loss of gain when a low value load resistor is connected to amplifier? 5.in what cases do v need to double clock a signal before presenting to a synchronous state machine? 6.why do v need to put a gate resistance in mosfet circuits? 7.you have a driver that derives a long signal & connects to an input device. at the input device ther is either overshoot,undershoot or signal threshold violations,what can be done to correct this problem?

I2C EEPROM [24C256] INTERFACING WITH FPGA IN

what is FPGA & ASIC?

i know the functionality of PAL,PLA. but i could't understand the logic blocks of cpld & fpga. Give some details & web address for the same. which book i have to follow? i have some doubts. 1.Is FPGA only for digital ckts? For analog circuit design what we r using? 2.What r the other technologies(like FPGA & ASIC)existing for IC Design(digital & Analog)? 3.What is EDA tools? 4.i need some details that hardware design Engineer must be known.

punch through implant

what is punch through implant? how will it affect the threshold voltage?

vhdl code for 8255

i want vhdl code for 8255 i want vhdl code for 8255

how to test a FPGA Look-up Lable ?

"An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing" which is an IEEE 2006 paper can any one guide me how to write the testing code for an FPGA in Verilog HDL.

fifo feature

How to verify fifo(like overflow r empty) feature ....? Can anybody give suggestions i need to verify this in system verilog language

wavelets-verilog program

please help me to write code for image comperession using haar wavelet in verilog

: latest trends in electronics

plz tell me some latest trends in electronics

use of configuration declaration

where we use configuration declaration in vhdl.Please send me the datas about SATRACK.andPPT too.

8086 microprocessor & assembly language

i need full notes on 8086 microprocessor &assemply language programming.

transistor as a switch

Transistor is ON when forward bias and OFF when reverse bias. Based on this property it is acting as a switch. I just want to know that In a IC there are millions of transistor, then how they are making both bias condition for each transistor.

electrodeless lamps

How electrodeless lamps work?

Lift Motion Control

plz send me the program of the Lift Motion Control by Microprocessor....Its urgent.......

vhdl encoder 8 to 3

i need in VHDL code the 8 to 3 encoder (encoder 8:3)...

how to write the code of image in verilog

how can i write the code of 512*512 grayscale image in verilog.

What is difference between 8085 and 8086 ??

The Intel 8085 is an 8 bit microprocessor created in 1977. The Intel 8086 is a 16 bit microprocessor created in 1978. The 8086 was the first chip to start the x86 architecture family. 8085 contains 16-bit address bus and 8-bit data bus 8086 contains 20-bit address bus and 16-bit data bus

final year project ideas

final year project lists availablity in any web site for indian engineering students.

Synthesis .....using Design Compiler

I am trying to synthesize a binary counter. The synthesis tool ( using Design Compiler from Synopsys) is generating counter using a full adder and some flip flops and some combinational logic. It is just a simple binary counter, so it should only use just flip flops and simple AND or OR like gates. I know that it depends on the coding style. Can somebody who have already faced such problem give the solution ?

Synthesis .....using Design Compiler

I am trying to synthesize a binary counter. The synthesis tool ( using Design Compiler from Synopsys) is generating counter using a full adder and some flip flops and some combinational logic. It is just a simple binary counter, so it should only use just flip flops and simple AND or OR like gates. I know that it depends on the coding style. Can somebody who have already faced such problem give the solution ?

How to generate subckt file and device model

i am working on an EDA tool which takes subckt files and device model files of a cell (circuit) in CMOS form as input and characterizes it . Is there any way or tool that take schematic of the circuit as input and give me these files in spice format so that i can characterize it with my tool.?????

How to generate subckt file and device model

i am working on an EDA tool which takes subckt files and device model files of a cell (circuit) in CMOS form as input and characterizes it . Is there any way or tool that take schematic of the circuit as input and give me these files in spice format so that i can characterize it with my tool.?????

Microprocessor Assingment BCA-3SEM

Write a program to convert a 2-digit BCD number into hexadecimal.

Could u let me know the working of IC UM66, its pin diagram, and working of IR MUSIC TRANSMITTER AND RECEIVER using IC UM66....

Could u let me know the working of IC UM66, its pin diagram, and working of IR MUSIC TRANSMITTER AND RECEIVER using IC UM66....

IR MUSIC TRANSMITTER AND RECEIVER

Could u let me know the working of IC UM66, its pin diagram, and working of IR MUSIC TRANSMITTER AND RECEIVER using IC UM66....

Lift Motion Control

send me the program of the Lift Motion Control by Microprocessor

HELP ME IN NEED OF PAPERS ON VLSI NEW DEVICE

I REALLY DONT KNOW WHERE TO GET THE INFO BASED ON VLSI .PLEASE HELP ME OUT.

read .csv file in to verilog file

pl. read .csv file in to verilog file

Celtic Noise report

can anyone get me seltic Noise report, uploaded.

Significance of Global skew

tell me significance of Global skew

verilog tutorial

Best tutorial for verilog tutorial
verilog tutorial made for all.
what engineering students require from it
what professional require from it http://vlsiforum.brinkster.net
Needs feed back what they need from verilog tutorialhttp://projectfeedback.brinkster.net
extensive workout result good verilog tutorial for you

VHDL code for Reed Solomon encoder and decoder

need VHDL code for RS(7,3),VHDL code for RS encoder too. can anyone help in this regard

89c51 ic

plz give me information abt 89c51 ic and it's application

cts spec generation

what are the mandatory inputs needed to generate clock tree specification file with encounter and how to generate clock tree spec file for perticular design

vhdl source code required

i need vhdl code for the following titles........ plz do this help, i need urgently, at the maximum those who know any 1 frm this also, plz send the source code....
1.FPGA-based UDP/IP stacks parallelism for embedded Ethernet connectivity 2.Design and Implementation of CDMA based Communication System in FPGA 3.UART Module for Real Time Application 4.Design and Implementation of 8051 Microcontroller in FPGA 5.Design and Implementation of PIC Microcontroller in FPGA 6.Design and Implementation of RISC Microcontroller in FPGA 7.Design and Verification of Inter IC (I2C) bus controller 8.Speed and Direction control of Stepper Motor Using FPGA 9.Design a Low Power 16-bit Booth Multiplier in FPGA 10.Improving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic 11.Design a High Speed First-in First-out (FIFO) in FPGA 12.Digital Design of DS-CDMA Transmitter and Receiver Using VHDL and FPGA 13.Design and Implementation of RSA Algorithm on FPGA 14.Design and Implementation of 8085 Microprocessor in FPGA

Please correct my KeyBoard Interface code

I am interfacing the keyboard with LCD on spartan-3e kit every thing is going well but when i dump the code on the kit to check it i am facing a problem: The problem is when i am typing the keyboard(KB) characters each and every character is getting displayed but on the same address that is, when i press A on KeyBoard it is displayed on the 00(1st) location on the LCD screen & later when i press B it is also displayed on the same 00(1st) location on the LCD screen by overwrighting A (but it must be displayed next to A).Can any one please fix my code

Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity KB_2 is Port ( FPGAclk,rst : in STD_LOGIC; Lcd_on : in STD_LOGIC; KB_Clk : inout STD_LOGIC; KB_Data : inout STD_LOGIC; sf_ce0 : out STD_LOGIC; rs : out STD_LOGIC; rw : out STD_LOGIC; en : out STD_LOGIC; q_LED : out STD_LOGIC_VECTOR (7 downto 0); q : out STD_LOGIC_VECTOR (3 downto 0)); end KB_2; architecture KB_2 of KB_2 is --********************************************************************************-- --**************************KEY BOARD SIGNAL DECLARATION**************************-- --********************************************************************************-- signal KBD_Temp : STD_LOGIC_VECTOR (7 downto 0):="00000000"; signal KBD_Temp2 : STD_LOGIC_VECTOR (7 downto 0):="00000000"; signal count_KB : INTEGER range 0 to 43; --********************************************************************************-- --**************************LCD SIGNAL DECLARATION********************************-- --********************************************************************************-- signal lcd_temp : STD_LOGIC_VECTOR (5 downto 0); signal lcd_stuff : STD_LOGIC_VECTOR (6 downto 0) := "0000000" ; signal lcd_count : STD_LOGIC_VECTOR (26 downto 0):= "000000000000000000000000000"; signal lcd_en : STD_LOGIC := '0' ; signal b : STD_LOGIC := '1' ; begin --**********************************************************************************-- --****************************Scan Code Detection Process*************************-- --**********************************************************************************-- Process Begin wait until KB_Clk='0' and KB_Clk'event; count_KB <= count_KB+1; if (count_KB >= 1 and count_KB < count_kb ="10)" fpgaclk="'1'">KBD_Temp2<=X"41"; --A when X"32"=>KBD_Temp2<=X"42"; --B when X"21"=>KBD_Temp2<=X"43"; --C when X"23"=>KBD_Temp2<=X"44"; --D when X"24"=>KBD_Temp2<=X"45"; --E when X"2B"=>KBD_Temp2<=X"46"; --F when X"34"=>KBD_Temp2<=X"47"; --G when X"33"=>KBD_Temp2<=X"48"; --H when X"43"=>KBD_Temp2<=X"49"; --I when X"3B"=>KBD_Temp2<=X"4A"; --J when X"42"=>KBD_Temp2<=X"4B"; --K when X"4B"=>KBD_Temp2<=X"4C"; --L when X"3A"=>KBD_Temp2<=X"4D"; --M when X"31"=>KBD_Temp2<=X"4E"; --N when X"44"=>KBD_Temp2<=X"4F"; --O when X"4D"=>KBD_Temp2<=X"50"; --P when X"15"=>KBD_Temp2<=X"51"; --Q when X"2D"=>KBD_Temp2<=X"52"; --R when X"1B"=>KBD_Temp2<=X"53"; --S when X"2C"=>KBD_Temp2<=X"54"; --T when X"3C"=>KBD_Temp2<=X"55"; --U when X"2A"=>KBD_Temp2<=X"56"; --V when X"1D"=>KBD_Temp2<=X"57"; --W when X"22"=>KBD_Temp2<=X"58"; --X when X"35"=>KBD_Temp2<=X"59"; --Y when X"1A"=>KBD_Temp2<=X"5A"; --Z when X"0E"=>KBD_Temp2<=X"60"; --` when X"16"=>KBD_Temp2<=X"31"; --1 when X"1E"=>KBD_Temp2<=X"32"; --2 when X"26"=>KBD_Temp2<=X"33"; --3 when X"25"=>KBD_Temp2<=X"34"; --4 when X"2E"=>KBD_Temp2<=X"35"; --5 when X"36"=>KBD_Temp2<=X"36"; --6 when X"3D"=>KBD_Temp2<=X"37"; --7 when X"3E"=>KBD_Temp2<=X"38"; --8 when X"46"=>KBD_Temp2<=X"39"; --9 when X"45"=>KBD_Temp2<=X"30"; --0 when X"55"=>KBD_Temp2<=X"3D"; --= when X"4E"=>KBD_Temp2<=X"2D"; --- when X"54"=>KBD_Temp2<=X"5B"; --[ when X"5B"=>KBD_Temp2<=X"5D"; --] when X"4C"=>KBD_Temp2<=X"3B"; --; when X"52"=>KBD_Temp2<=X"27"; --' when X"41"=>KBD_Temp2<=X"2C"; --, when X"49"=>KBD_Temp2<=X"2E"; --. when X"4A"=>KBD_Temp2<=X"2F"; --/ when X"29"=>KBD_Temp2<=X"20"; --space when others=>null; end case; q_LED <= KBD_Temp2; end if; end process; --********************************************************************************-- --++++++++++++++++++++++++++LCD Initialisation Process++++++++++++++++++++++++++++-- --********************************************************************************-- process begin wait until FPGAclk ='1' and FPGAclk'event; lcd_count <=lcd_count + "0000000000000000000000001"; sf_ce0 <= '1'; case lcd_count(24 downto 18) is --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- --*************************LCD Commands for Initialisation************************-- --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- when "0000000" => lcd_temp <= "000011";--3 when "0000001" => lcd_temp <= "000011";--3 when "0000010" => lcd_temp <= "000011";--3 when "0000011" => lcd_temp <= "000010";--2 when "0000100" => lcd_temp <= "000010"; when "0000101" => lcd_temp <= "001000";--28 when "0000110" => lcd_temp <= "000000"; when "0000111" => lcd_temp <= "000110";--06 when "0001000" => lcd_temp <= "000000"; when "0001001" => lcd_temp <= "001100";--0c when "0001010" => lcd_temp <= "000000"; when "0001011" => lcd_temp <= "000001";--01 when "0001100" => lcd_temp <= "001000"; when "0001101" => lcd_temp <= "000000";--80 1st line addr when "0001110" => lcd_temp <= "000000"; when "0001111" => lcd_temp <= "001100";--return cursor home --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- --*************************Sending Data To LCD************************************-- --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- when "0011000" => lcd_temp(5 downto 4) <= "10"; lcd_temp(3 downto 0) <=KBD_Temp2(7 downto 4); when "0011001" => lcd_temp(5 downto 4) <= "10"; lcd_temp(3 downto 0) <=KBD_Temp2(3 downto 0); when "0011010" => lcd_temp(5 downto 4) <= "10"; lcd_temp(3 downto 0) <="0010"; when "0011011" => lcd_temp(5 downto 4) <= "10"; lcd_temp(3 downto 0) <="0000"; -- space when "0011100" => lcd_temp(5 downto 4) <= "10"; lcd_temp(3 downto 0) <="0010"; when "0011101" => lcd_temp(5 downto 4) <= "10"; lcd_temp(3 downto 0) <="0000"; -- space when others =>lcd_temp <= "010000"; end case; --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- --*************************LCD enable pin operation & assigning data to output****-- --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- b<= lcd_count(17) or lcd_count(16); lcd_en <= b and not lcd_temp(4);--lcd enable pin process lcd_stuff(6) <= lcd_en; lcd_stuff(5 downto 0) <= lcd_temp; (en,rs,rw,q(3),q(2),q(1),q(0)) <= lcd_stuff; end process; end KB_2;

verilog code contest http://vlsiforum.brinkster.net

http://vlsiforum.brinkster.net
VERILOG code contest
very competitive have fun
graduate engineer studying should follow it .learn and skill to become expert and reach to any MNC.

VHDL code contest http://vlsiforum.brinkster.net

http://vlsiforum.brinkster.net
VHDL code contest
very competitive have fun
graduate engineer studying should follow it .learn and skill to become expert and reach to any MNC.

DRINKING WATER ALARM

want to know a detail about DRINKING WATER ALARM circuit describtion

DSP the application of convolution code

primitative with datastructures

what is primitative with datastructures ?

object detecting sensor

Is there any sensor which can detect any object placed anywhere within that sensor range?

Answer of fulladder

Advantages of full adder i want to know.

different types of adders

different types of adders

VHDL code for Reed Solomon encoder and decoder

need VHDL code for RS(7,3)can anyone help in this regard?

applications of vlsi

what are the basic applications of vlsi technology

Reed solomon(255,239) encoder in VHDL code

looking for a rs encoder code in VHDL. i dont want to use ISE cores. can anyone help

8 8-bit ALU register

The task is to design a component which could be used in the core of a microprocessor:
We shall call this Register_ALU: • the design will contain 8 8-bit registers which can be loaded from an external input; • the design will contain a block of logic which will have two 8-bit inputs A[7..0] and B[7..0], and will produce one 8-bit output C[7..0]; • the output will be formed as o A and B, or o A or B, or o A plus B, or o A minus B; • the operation {logical and, logical or, arithmetic plus, arithmetic minus} will be selected by an external input to the design, called Op_Code[1..0]; • the output C[7..0] can be o loaded back into one of the eight internal registers, or o read externally.
please send me the code for this problem

super buffer with interconnects

want to do my thesis in super buffer with interconnects using EDA tools,and the technology to be used is below 180 nm. please guide me.

size NMOS and PMOS to increase Vt

How do we size NMOS and PMOS transistors to increase the threshold voltage

I2C protocol implementation in verilog & VHDL

required I2C protocol implementation in verilog & VHDL. first preference is verilog. vhdl will also do.

Scaling models formulated by Dennard

tell link sites and textbooks where I can find a detailed explanation of the scaling models formulated by Dennard

differential to single ended converter

explain me about the D2S structure i.e,differential to single ended ckt..

computer networking

what is difference between tcp and ip?

output impedence of cs amplifier

how to calculate the output impedence of a cs amplifier using pspice ??? i have some idea but I just need to check whether its right so can anyone please guide??

output impedence of cs amplifier

how to calculate the output impedence of a cs amplifier using pspice ??? i have some idea but I just need to check whether its right so can anyone please guide??

output impedence of cs amplifier

how to calculate the output impedence of a cs amplifier using pspice ??? i have some idea but I just need to check whether its right so can anyone please guide??

copper bonding technology

what is copper bonding technology ?

cadence virtuso -spectre simulator

. i am using for design cadence virtuso,( schematic design),for simulating i am using spectere, can you tell me how to give pulse either 0 or 1 directly irrespective of pulse wave forms.

Related with memory

Please send me detail about different type of memory,there types,how to implement any dynamic memory using verilog code for dump in the FPGA.

iam using spartan II fpga kit.i have to give hall sensor output(nothing but a square pulses) to the fpga input ports.so what is the max i/p value(i.e square pulse voltage 2 volts or 3 volts) i can give to the kit with out damaging i/p ports.

iam using spartan II fpga kit.i have to give hall sensor output(nothing but a square pulses) to the fpga input ports.so what is the max i/p value(i.e square pulse voltage 2 volts or 3 volts) i can give to the kit with out damaging i/p ports.

How to download VHDL code into FPGA

I had a problem downloading my VHDL code to FPGA. I did my simulation with my VHDL code.Now i need to download it into FPGA and display the output on 7segment display.I understand that in order to download, i need to create a new top level entity(port SW1,CLK,LED7SEG) and not using my previous top level entity with 2inputs and 1output(simulation).Only after that i can do my pin assignment,rite?Can anyone provide me with a new top level entity(built in with 7segment decoder code) example?

fpga code of dmb-th transmitter for sail

I developed dmb-th (chinese standard of DVB) tranditter with xilinx's fpga,and fpga code is for sail

diff b/w virtual memory n cache memory

What s the diff between a virtual memory and cache memory?

Sending to/receiving data from USB port

I've been trying to write a simple program in C/C++ under WinXp with VC++ 8.0 that allows me to send to/receive data from to the usb port, so that I can be able to control a digital device. If one of you has an idea about how to do it or knows a certain sorce of material about it, please help me.

Regarding selecting my major ANALOG or DIGITAL DEG

I am doing my MS in vlsi and i have to select my major this fall.i am confused between analog and digital design.please suggest which one has more scope from the job point of view.And i have no particular inclination towards any of these. i am good at both but now i have to select one, only thing is that analog is bit more sifficult than digital in my univ but dats not the point. i am just looking for the one which can fetch me more calls. please suggest me in this coz i knw u guys knw more than i knw.

transmission gate in cmos design

I am working on a design where I needed to isolate two different circuits.I was suggested to use transmission gate but,the transmission gate is leaking the voltage even when it is off.Can anyone suggest me the ideal isolator by either customizing the transmission gate or completely different circuit.

JK flip flop gate level verilog code

can someone give me a gate level or RTL verilog code for JK flip flop? my outputs are always x.

JK flip flop gate level verilog code

can someone give me a gate level or RTL verilog code for JK flip flop? my outputs are always x.

application of 8086?

what is the application of 8086?

GSRC floorplan benchmark suite ?

can i get GSRCbenchmark suite n100, n200, and n300?

Is Generate statement is Synthasizable

I tried to get the resource utilisation of a given design. I have instantiate the component number of times with generate statement.then i done the synthesis in xilinx tool but i got the final report mentioned bellow.So please give me the solution to get the utilization of slices.
Selected Device : 2v40cs144-6 Number of Slices: 0 out of 256 0% Number of IOs: 18 Number of bonded IOBs: 18 out of 88 20% -------------------------------------------------------------------------------------- Design: library IEEE; use IEEE.std_logic_1164.all; entity systolic_algorithm is generic ( DATA_WIDTH : integer := 8 ); Port( clk : in std_logic; en : in std_logic; din : in std_logic_vector(DATA_WIDTH-1 downto 0); dout : out std_logic_vector(DATA_WIDTH-1 downto 0) ); end systolic_algorithm; architecture Behavioral of systolic_algorithm is component systolic_pe is generic ( DATA_WIDTH : integer := 8 ); Port( clk : in std_logic; en : in std_logic; din : in std_logic_vector(DATA_WIDTH-1 downto 0); dout : out std_logic_vector(DATA_WIDTH-1 downto 0) ); end component; constant N : integer := 3; type locsignal_type is array(N-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0); signal locsignal : locsignal_type; begin u0: for i in 0 to N-1 generate u10: if (i = 0) generate u11: systolic_pe port map( clk => clk, en => en, din => din, dout=> locsignal(0)); end generate u10; u20: if ((i > 0) and (i < clk =""> clk, en => en, din => locsignal(i-1), dout=> locsignal(i)); end generate u20; u30: if (i = N-1) generate u33: systolic_pe port map( clk => clk, en => en, din => locsignal(i), dout=> dout); end generate u30; end generate u0; end Behavioral;

architecture and pin configuration of 80386

architecture and pin configuration of 80386 microprocessor

regarding antenna radiation

want to ask you in details about radiation mechanism of a)single wire b)two wire c)dipoles d)current distribution on a thin wire antenna

vhdl code for modified booth multiplier

needed vhdl code for modified booth multiplier

block statement

i have written a code with block statement. when i run this statement it shows some error

multiplying two matrix in verilog with the help of

how can i write a program in verilog by which i can multiply 3*3 matrix to another 3*3 matrix . plz send me a simple program how can i define a matrix using array plz tell me how can i creat a 2 d array in verilog

cadence virtuso -spectre simulator

Hi dear users im srinivas. i am using for design cadence virtuso,( schematic design),for simulating i am using spectere, can you tell me how to give pulse either 0 or 1 directly irrespective of pulse wave forms. please send me any idea

Could u let me know the working , circuit description and application of IR music transmitter and receiver using ICum66 in detail.

COMPUTER SYSTEM

3 ques. 1> difference between computer archtecture and organization, 2>what is vlsi system? 3>CPI, MIPS and the relation between CPI & MIPS.

masm pgms

program to make pascal's triangle if anybody knws it plz send me

Asking for the circute diagram of w200 sonyericson

send the circuite diagram of sonyericson W200 model ,

cdma coding

cdma coding in which we use the tata cdma in rim handset or any other cdma handset.

object detecting sensor

Is there any sensor which can detect any object placed anywhere within that sensor range? please send me the link of website where i can get the knowledge regarding that sensor.

Process sequence for fabricating Poly Gate

I am wondering the "correct" sequence for fabricating a layer of gate oxide and poly gate on a bare silicon substrate. The substrate is also implanted with boron. So this is my thinking: bare silicon substrate -> coated with photoresist -> selectively exposed -> exposed region implanted with boron -> then strip the unexposed photoresist. At this point, I am confused on how to proceed to build the layer of gate oxide on which the poly gate is directly built. I will appreciate guidance on how to proceed to build the structure further.

0.35 um Technology Design Guide

I am working on 0.35 um Technology Design Rules. Can anyone pls forward me such document which may help me in constructing so.

define a matrix in verilog

want to implement duetcsh jozsa problem of quantum mechanics on fpga so i want to know how we can define a matrix in verilog and how can i multiply two matrix in verilog

simple 16 bit processor code in vhdl

hi everyone need to simple 16 bit the processor tails in vhdl. please help me

SDRAM PROBLEM

Hi I am using Kingston 512MB SDRAM for my XUP virtex 2 pro development board. I am working on image filtering where I have to transfer the image file to the SDRAM and then filter it by bring the data to the BRAM's. I am struck off into following steps: 1. How can I send a whole image file to the SDRAM. I can put some data on the SDRAM using the EDK C code which is as follows #define XPS_MEM_RAM 0x60000000 // this was the starting address of the SDRAM as //provided by the EDK when I added it to my system Xuint32 *RAM; RAM=XPS_MEM_RAM; RAM[i]=0x12345678; but how to send a full file... Also I am not sure whether the procedure i followed is completely correct??? 2.How can i bring my data(which is in SDRAM) to the BRAM. Can i add BRAM to my EDK system as i added SDRAM... If so how??? I also tried to access the SDRAM with VHDL code but it was quiet complicated. I also heard about SDRAM controller but didn't found any for my SDRAM. Please suggest me something for any of the two problems.

Modelling Transmission Lines

Modelling Transmission Lines

SystemVerilog

Iam working on systemverilog verification since m beginner facing difficulty in running test and writing testbench if anybody have some material r books on systemverilog

Voltage Source & capacitor, Voltage source & Diode

what will be the Output voltage when a Capacitor is connected to a voltage source in series. The circuit is not closed Figure ----------. Vin vout1 ____________. Similarly instead of a capacitor if a diode is connected what will be the output ------ -> ----. Vin vout2 ______________. ------ <- ----. Vin vout3 ->,<- are diodes ______________.

Embedded Systems

in future the growth and offers in embedded..

vhdl for nco(DDS)

urgently required a dds signal genarator vhdl description to implement it on spartan3 xilinx fpga using xilinx 8.2.I want all the files needed to implement it.And How can I use lpm components(or instead of them) like lpm rom,lpm ff,lpm add sub in xilinx ise8.2?

VHDL code for CIC Decimation

I need a general code for vhdl cic decimator for factor 5. My Fs is 400Mhz and IF is 5Mhz.

cts spec generation

what are the mandatory inputs needed to generate clock tree specification file with encounter and how to generate clock tree spec file for perticular design

need guidence to give connstraints

need to learn to give constraints to a verilog model using xylinx sparten 2 xst200 pq208

need guidence to give connstraints

need to learn to give constraints to a verilog model using xylinx sparten 2 xst200 pq208

FINAL YEAR PROJECTS IDEAS

PROJECTS for BE,MCA,electronics,communication get an idea let us discuss to prepare well on this such a vast topics to prepare well for PROJECT work.Do some good job to become industry ready in real.

any one have MSK source code

really need the msk vhdl source code..pls help

need matlab code or vhdl code

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