Timing constraints in XILINX ISE

pl explain me about timing constraints in xilinx ISE.
exactly wat am looking is how to apply timing constraints.
if possible explain brief description for counter/ff/or simple gates also.
xi

zero padding

i m designing an OFDM transceiver in xilinix system generator. i took data and modulated the data using QPSK. then before giving my data to IFFT i need to do its zero padding. my incoming data is at the rate of 800 samples per sec. i want to take 1st 400 samples and store them. i tried to use RAM of depth 400(i dont know i m right or wrong), then next 400 samples in another RAM. and now i want to add 224 zeros in between these two data samples of 400. My data rate has been increases from 800 samples/sec to 1024. How can i store this higher sample rate. and how can i implement my problem in system generator. can i use FIFO any where.

Xilinx FPGA clock division for UART

I am using a Spartan3 Xilinx FPGA and I want to implement a UART module. The frequency of the crystal on board is 50MHz and I need to divide this frequency.
OK, one way is to implement a counter and use its output as a clock.
But in Spartan3 there are some specific clock generation modules that provides some advantages compared to the counters (clock tree routing, not much skew, phase shift and more..).
From what I saw, these modules cannot divide a clock frequency by more than 16.

Is there some way to use those modules (and not only counters) in order to divide the 50MHz clock with a bigger number (ie 256) and distribute it to the rest circuit?

fpga implementation of reed solomon decoder

can anyone send me the vhdl coder using berlekamp massey key equation for decoder for synthesizing and implement on xilinx FPGA with virtex version-4 and series 35 along with explanation....

Keep_hierarchy

What is keep hierarchy in xilinx xst for what purpose it is used?

vhdl for nco(DDS)

urgently required a dds signal genarator vhdl description to implement it on spartan3 xilinx fpga using xilinx 8.2.I want all the files needed to implement it.And How can I use lpm components(or instead of them) like lpm rom,lpm ff,lpm add sub in xilinx ise8.2?

DES encryption decryption

please send me DES encryption and decryption source code in vhdl which could run on xilinx2 simulator. I shall be grateful if u could post the code as early as possible.