Showing posts with label FPGA. Show all posts
Showing posts with label FPGA. Show all posts
Friday, August 13, 2010
vhdl code to interface fpga with lcd
pl tell me the steps to be followed while coding or posting the code for interfacing a virtex II pro fpga with lampex lm16200 lcd.
Wednesday, June 2, 2010
Xilinx FPGA clock division for UART
I am using a Spartan3 Xilinx FPGA and I want to implement a UART module. The frequency of the crystal on board is 50MHz and I need to divide this frequency.
OK, one way is to implement a counter and use its output as a clock.
But in Spartan3 there are some specific clock generation modules that provides some advantages compared to the counters (clock tree routing, not much skew, phase shift and more..).
From what I saw, these modules cannot divide a clock frequency by more than 16.
Is there some way to use those modules (and not only counters) in order to divide the 50MHz clock with a bigger number (ie 256) and distribute it to the rest circuit?
OK, one way is to implement a counter and use its output as a clock.
But in Spartan3 there are some specific clock generation modules that provides some advantages compared to the counters (clock tree routing, not much skew, phase shift and more..).
From what I saw, these modules cannot divide a clock frequency by more than 16.
Is there some way to use those modules (and not only counters) in order to divide the 50MHz clock with a bigger number (ie 256) and distribute it to the rest circuit?
Thursday, May 20, 2010
fpga implementation of reed solomon decoder
can anyone send me the vhdl coder using berlekamp massey key equation for decoder for synthesizing and implement on xilinx FPGA with virtex version-4 and series 35 along with explanation....
Saturday, May 8, 2010
guidance program
iwant program in "verilog" to giude amissile ,IF the input of target are none {Module Guidance(trgt_distination,trgt_velocity,angle).
THE MISSLE IS GOING ON{x,y}axis (that mean we used the Laws of linear motion )
(by using fpga )
THE MISSLE IS GOING ON{x,y}axis (that mean we used the Laws of linear motion )
(by using fpga )
how to implement vhdl coding on fpga
i am doing booth encoded wallace tree multiplier(32 bit) using VHDL/VERILOG .
but i don't know how to implement vhdl code on fpga board .
i am using SPARTAN 3E KIT (FPGA BOARD).
please send me the steps how to run the coding on fpga board FOR 32 BIT VHDL CODE.
but i don't know how to implement vhdl code on fpga board .
i am using SPARTAN 3E KIT (FPGA BOARD).
please send me the steps how to run the coding on fpga board FOR 32 BIT VHDL CODE.
Friday, May 7, 2010
Keypad Scanner & LCD
I am trying to program the FPGA such that it takes inputs from HEX Keypad & show the output on LCD. Ex. pressing 4 5 6 9 8 on Keypad should display 45698 on the lcd.
suggest me the logic or some sample codes in VHDl to guide me through..
suggest me the logic or some sample codes in VHDl to guide me through..
Monday, April 26, 2010
Keypad Scanner & LCD
I am trying to program the FPGA such that it takes inputs from HEX Keypad & shows the output on LCD. Expressing 4 5 6 9 8 on Keypad, should display 45698 on the lcd. suggest me the logic or some sample codes in VHDl to guide me
7segment
I need to display different numbers on the 7segments that are on the fpga according to the input I have. For example if I want to display the number 250, 2 on the 1st segment, 5 on the 2nd and 0 on the 3rd... How do I do it in VHDL pls?
Till now I am only capable of displaying the same number on all of the segments. My fpga is a spartan 3e-100
If anyone could help me I would really appreciate.
Till now I am only capable of displaying the same number on all of the segments. My fpga is a spartan 3e-100
If anyone could help me I would really appreciate.
Monday, April 5, 2010
7segment
I need to display different numbers on the 7segments that are on the fpga according to the input I have. For example if I want to display the number 250, 2 on the 1st segment, 5 on the 2nd and 0 on the 3rd... How do I do it in VHDL pls? Till now I am only capable of displaying the same number on all of the segments. My fpga is a spartan 3e-100. Anyone Pl help me.
Sunday, October 4, 2009
What is better FPGA or CPLD?
which 1 is betterfpga or cpld and why? and, why there grade speeds r mentioned as negative values?
Tuesday, September 29, 2009
dumping the vhdl code into 2 vertex II-pro kits
I am using two vertex II pro kits.I need to dump some modules into one fpga and some other into another fpga,can you tell me how to dump the code into two fpgas.
Friday, September 11, 2009
Wednesday, August 26, 2009
electronic voting machine
i am trying to implement an Electronic Voting Machine in vlsi. can anyone plz give me an idea how to start with it or suggest some website where they can give me details about the same. i want my result(no. of votes gained by each candidate) to be displayed on 7 segment of my FPGA board. so can anyone highlight me how to write the code for the same.
www.asic.co.in
I found this new site www.asic.co.in it contains real time interview questions(FPGA, RTL, CMOS,SYNTHESIS) compiled from many design engineer interview experience a must see and read for every VLSI engineer.
Friday, August 21, 2009
netbook and vlsi applications
is it possible to run vlsi/fpga/embedded tools/applications in netbook? what about performance,speed on running these programs?
Subscribe to:
Posts (Atom)