verilog code

please provide me the verilog code for Path selector in Dual node interconnected SONET/SDH Ring for BLSR.

digital watch design

I need verilog code to design a watch and also I want its design blocks

8 bit super register

I WANT A VERILOG CODE FOR UNIVERSAL REGISTER
It has 5 inputs: clk, data_in , control, data_sh_r and data_sh_l. The first input, clk, is the clock input where any new operation takes place at the rising edge of this clock signal. The second input, data_in, is an 8 bit input used to load a new data into our register. The third input, control, is a 3 bit input to determine which operation of the eight operations to be performed. The last two inputs, data_sh_r and data_sh_l, each is a 1 bit input used as a shift-in bit when shifting right or left respectively. The Register has two outputs. The first output is 8 bit representing the output data from the register, while the second output is a single bit which is ‘1’ when the output of the register is “00000000” and is ‘0’ otherwise.

Depth to Address width in verilog

I am reading this topic "verilog code for RAM and FIFO" in which address width of the address bus is given as - parameter ADDR_BUS_WD = 1>>DEPTH; //Address bus width My question is, why is this supposed to work? The reason I ask is because it is not working for me in Aldec's Riviera Pro tool.

Verilog code for RAM

(1) I am trying to design a 128bytes RAM similar to tht of 8051 using verilog... plz

i need a verilog code for braille code

i need a program/code for braille code..

E123 MUX / DEMUX Transceiver IP Core

please frd me to verilog code( which can be synthesized ) or block diagram or any details regarding the below mentioned.
The E123MUX is a VLSI core that provides the E13 functions needed to multiplex and demultiplex 16 independent E1 signals to and from an E3 signal that conforms to the ITU-T G.751 Recommendation. The E1 and E3 signal an interface is NRZ only. The E123MUX can also be configured to operate as an E12 or E23 multiplexer and demultiplexer. Sixteen E1 signals can be multiplexed and demultiplexed to and from four E2 signals that conform to the ITU-T G.742 Recommendation. Alternatively, four E2 signals can be multiplexed and demultiplexed to and from one E3 signal. The E2 signal interfaces are also NRZ only. Any 4 lines of 16 E1s can be multiplexed in one E2.The E123MUX uses memory locations for setting control bits and reporting status information. Microprocessor 8-bit bus provides the access of memory locations of E123MUX/DEMUX.
Feature Summary: E1 (2048 kbit/s) multiplexer/demultiplexer for ITU-T Recommendations: G.742 (8448 kbit/s E2 frame format) G.751 (34368 kbit/s E3 frame format) Multiplexer/demultiplexer converts: 16 E1s to/from 1 E3 (E13 skip mux), or 16 E1s to/from 4 E2s, or 4 E2s to/from 1 E3 (E12/E23 split mux) Select any 4 E1s to make one E2 through microprocessor interface Generates and detects E2 and E3 alarms Microprocessor input/output 8-bit bus provides split mode Intel interface

verilog code for 5 bit sequence detector

Wanted verilog code for the sequence 11010

verilog code 4 low power shift-and-add multiplier

needed verilog code 4 low power shift-and-add multiplier

sine wave o/p of given frequency using DAC

want to generate the sine wave of certain frequency using DAC,verilog code too needed

Verilog code for 8251 USART circuit

Does someone have an either behavioral, or structural description of the 8251 USART circuit in Verilog? I need it for a university-project.

verilog code for USB 2.0

need verilog code for protocol of USB 2.0

verilog code 4 4-bit alu

can anyone give me a 4-bit alu verilog code?

E123 MUX / DEMUX Transceiver IP Core

please frd me to verilog code( which can be synthesized ) or block diagram or any details regarding the below mentioned. The E123MUX is a VLSI core that provides the E13 functions needed to multiplex and demultiplex 16 independent E1 signals to and from an E3 signal that conforms to the ITU-T G.751 Recommendation. The E1 and E3 signal an interface is NRZ only. The E123MUX can also be configured to operate as an E12 or E23 multiplexer and demultiplexer. Sixteen E1 signals can be multiplexed and demultiplexed to and from four E2 signals that conform to the ITU-T G.742 Recommendation. Alternatively, four E2 signals can be multiplexed and demultiplexed to and from one E3 signal. The E2 signal interfaces are also NRZ only. Any 4 lines of 16 E1s can be multiplexed in one E2.The E123MUX uses memory locations for setting control bits and reporting status information. Microprocessor 8-bit bus provides the access of memory locations of E123MUX/DEMUX. Feature Summary: E1 (2048 kbit/s) multiplexer/demultiplexer for ITU-T Recommendations: G.742 (8448 kbit/s E2 frame format) G.751 (34368 kbit/s E3 frame format) Multiplexer/demultiplexer converts: 16 E1s to/from 1 E3 (E13 skip mux), or 16 E1s to/from 4 E2s, or 4 E2s to/from 1 E3 (E12/E23 split mux) Select any 4 E1s to make one E2 through microprocessor interface Generates and detects E2 and E3 alarms Microprocessor input/output 8-bit bus provides split mode Intel interface

exponential function code in vhdl

want urgently.please explain code in vhdl/verilog

need a simple code

can somebody plz give me a code in verilog that converts a 12 bit binary number into a decimal number.

verilog code of DES encryption

i am in urgent need of DES code in verilog. have made the code but i am not able to do the timing analysis .

Related with memory

Please send me detail about different type of memory,there types,how to implement any dynamic memory using verilog code for dump in the FPGA.

JK flip flop gate level verilog code

can someone give me a gate level or RTL verilog code for JK flip flop? my outputs are always x.

JK flip flop gate level verilog code

can someone give me a gate level or RTL verilog code for JK flip flop? my outputs are always x.