verilog code contest http://vlsiforum.brinkster.net

http://vlsiforum.brinkster.net
VERILOG code contest
very competitive have fun
graduate engineer studying should follow it .learn and skill to become expert and reach to any MNC.

VHDL code contest http://vlsiforum.brinkster.net

http://vlsiforum.brinkster.net
VHDL code contest
very competitive have fun
graduate engineer studying should follow it .learn and skill to become expert and reach to any MNC.

vhdl for nco(DDS)

urgently required a dds signal genarator vhdl description to implement it on spartan3 xilinx fpga using xilinx 8.2.I want all the files needed to implement it.And How can I use lpm components(or instead of them) like lpm rom,lpm ff,lpm add sub in xilinx ise8.2?

FINAL YEAR PROJECTS IDEAS

PROJECTS for BE,MCA,electronics,communication get an idea let us discuss to prepare well on this such a vast topics to prepare well for PROJECT work.Do some good job to become industry ready in real.

FINAL YEAR PROJECT USING VERILOG CODE

FINAL YEAR PROJECT USING VERILOG CODE NEED SOME IDEA THAT DOING BE FINAL YEAR PROJECT USING VERILOG CODE CAN EXCELL TO BECOME INDUSTRY READY.

FINAL YEAR PROJECT USING VHDL CODE

FINAL YEAR CODE USING VHDL CODE.NEED SOME IDEA WHERE CAN BE EXCELLED USING VHDL CODE TO BECOME INDUSTRY READY.DOING BE FINAL YEAR PROJECT

FINAL YEAR PROJECT

FINAL YEAR BE project