VHDL and VERILOG difference and HVL use like system verilog,SystemC,e,vera

WHat is the use of HVL and VHDL and Verilog diffrence and similarity,

How HVL helps validate HDL design!

SystemVerilog

Iam working on systemverilog verification since m beginner facing difficulty in running test and writing testbench if anybody have some material r books on systemverilog