Xilinx FPGA clock division for UART

I am using a Spartan3 Xilinx FPGA and I want to implement a UART module. The frequency of the crystal on board is 50MHz and I need to divide this frequency.
OK, one way is to implement a counter and use its output as a clock.
But in Spartan3 there are some specific clock generation modules that provides some advantages compared to the counters (clock tree routing, not much skew, phase shift and more..).
From what I saw, these modules cannot divide a clock frequency by more than 16.

Is there some way to use those modules (and not only counters) in order to divide the 50MHz clock with a bigger number (ie 256) and distribute it to the rest circuit?

clock division

need code for clock division in VHDL