BUILT IN SELF TEST FOR RAM

could you please help me in how to find the code for BUILT IN SELF TEST OF RAM in vhdl language please help me

Depth to Address width in verilog

I am reading this topic "verilog code for RAM and FIFO" in which address width of the address bus is given as - parameter ADDR_BUS_WD = 1>>DEPTH; //Address bus width My question is, why is this supposed to work? The reason I ask is because it is not working for me in Aldec's Riviera Pro tool.

Verilog code for RAM

(1) I am trying to design a 128bytes RAM similar to tht of 8051 using verilog... plz

USING RAM VHDL code

can anyone explain how the RAM work in vhdl code and I want 256-byte ram and how can I fill it from 0 to 255

USING RAM VHDL code

can anyone explain how the RAM work in vhdl code and I want 256-byte ram and how can I fill it from 0 to 255