Showing posts with label VERILOG. Show all posts
Showing posts with label VERILOG. Show all posts

Wednesday, September 1, 2010

93lc86c EEPROM

Please provide me 93lc86c EEPROM interfacing code either in verilog or vhdl

Friday, August 13, 2010

PRBS checker module in Verilog

how to code for a prbs checker and error injector module in verilog

Thursday, June 10, 2010

DIffernce Between VHDL & VERILOG

any one pl tell the differnce between verilog and Vhdl

Saturday, May 8, 2010

How to resimulate a verilog-A simulation?

I have simulated a verilog-A netlist using spectre.
I have the savetime file (*.srf) at 55us.
I want to re-simulate design from 55us to 100us.
While doing so, the verilog A models are giving wrong result.

Can anybody tell me how to re-simulate the design.

Monday, April 26, 2010

SAFER(Security And Fast Encryption Routine)algrthm

Is there any code for SAFER ALGORITHM in VHDL r in Verilog

Wednesday, October 28, 2009

Multiplier Code in Verilog

can anyone tell me how to write a code for a multiplier with two 16 bit inputs?

Monday, September 28, 2009

Reading Files in Verilog

Can anyone help me like how it should be done? I need to Read R G B values of each pixel from 3 separate file and Write the corresponding Y U V files separately.

Saturday, September 19, 2009

verilog hdl

verilog hdl codes for 4-bitadders,subtractors,counters,JK-flipflop,T-flipflop

Thursday, August 20, 2009

parallel in serial out

please give the parellel in serial out verilog program.

Tuesday, August 4, 2009

programs related to logical design

i need all programs related to logical design in verilog

Monday, August 3, 2009

Floating Point ALU

how can i generate code for floating point ALU (adder,subtractor & multiplier) in VERILOG? and also give the idea of synthesis report of it.

Wednesday, July 29, 2009

fifo feature

How to verify fifo(like overflow r empty) feature ....? Can anybody give suggestions i need to verify this in system verilog language

wavelets-verilog program

please help me to write code for image comperession using haar wavelet in verilog

Tuesday, June 23, 2009

FINAL YEAR PROJECT USING VERILOG CODE

FINAL YEAR PROJECT USING VERILOG CODE NEED SOME IDEA THAT DOING BE FINAL YEAR PROJECT USING VERILOG CODE CAN EXCELL TO BECOME INDUSTRY READY.

FINAL YEAR PROJECT USING VHDL CODE

FINAL YEAR CODE USING VHDL CODE.NEED SOME IDEA WHERE CAN BE EXCELLED USING VHDL CODE TO BECOME INDUSTRY READY.DOING BE FINAL YEAR PROJECT