FIFO Depth Means wat.?

If i get the FIFO depth as 2, then wat exactly it means....

Depth to Address width in verilog

I am reading this topic "verilog code for RAM and FIFO" in which address width of the address bus is given as - parameter ADDR_BUS_WD = 1>>DEPTH; //Address bus width My question is, why is this supposed to work? The reason I ask is because it is not working for me in Aldec's Riviera Pro tool.

fifo feature

How to verify fifo(like overflow r empty) feature ....? Can anybody give suggestions i need to verify this in system verilog language