edge trigger Master slave

I want to konw if +ve edge triggering possible in master slave and also Is edge triggerin possible in JK flip flop

Blocking & Non Blocking

when I code Flip-Flop or Shift Registers. The data latches on the flip-flop on the next edge of the clock but not on the desired clock edge . Why does this happen . I even tried different combinations with blocking and non-blocking statements "= ,<=" The results are the same .

setup and hold tim

Why is the set up and hold time required at all....i mean where is this extratime helped in the circuit..can u explain w.r.t to the cmos structure of the Flip Flop...as in is that some cap requires that or something else which requires that