93lc86c EEPROM

Please provide me 93lc86c EEPROM interfacing code either in verilog or vhdl

secret bell

give me some idea about secret bell project?

stick diagram for 2:1 multiplexer

how to write stick diagram and layout for 2:1 multiplexer

plz help me out..

how to write vhdl code for pulse width and pulse repetation interval .
in case of pulse width we need to find the pulse width of the pulse

Regarding schmoo plots

What are schmoo plots?

Liao wong algorithm

which edges are to be considered as forward path and feedback path in a given graph for calculating longest path using liao wong algorithm.pl explain about ordering in binary decision diagrams ?

mcu or mp

even the mcu has the more advantage than the mp y don we use the mcu instead of mp in our pcs and labtops????

Losses of Bytes in TEMAC transmitting

We are targetting Spartan6 device.package is LX45.we want to transmit data through ethernet.But we are lossing bytes during transmitting.We are using IPCORE.Can any one guess the reason?

FELICS ALGORITHM

doing project in loss less image compression using VLSI oriented FELICS Algorithm help me to write code in Verilog.i need some ideas to implement

7490 counter

how to use 7490 counter and the internal architecture

code for a transfer function

i want the vhdl code for a two zeros two pole transfer function

FIFO Depth Means wat.?

If i get the FIFO depth as 2, then wat exactly it means....

single wire radiation

how radiation is achieved?

vhdl code to interface fpga with lcd

pl tell me the steps to be followed while coding or posting the code for interfacing a virtex II pro fpga with lampex lm16200 lcd.

PRBS checker module in Verilog

how to code for a prbs checker and error injector module in verilog

Reconvergence

what recnvergence mean in eda

ihld

needed timingdigram of ihld

cmos design challenges in the Nanotechnology era

please give me breaf description about cmos design challenges in nanotechnology era

fpga,asic

please give me the details fpga design in bus interface i.e:1553

BUBBLE

how to sort using 8086 micro proccessor

how to view layout in cadence virtuoso with lef?

I have LEF, DEF, LIB, PLIB, DB, etc. all files from SoC and such but no gds. These files are from ARM with general I/O and pad cell but I need to see them with virtuoso. One person told me maybe a synopsys function called fdi2gds on the lef file, but I'm not sure how to use it.

operating frequency of VLSI

what is the operating frequency of VLSI?

Timing constraints in XILINX ISE

pl explain me about timing constraints in xilinx ISE.
exactly wat am looking is how to apply timing constraints.
if possible explain brief description for counter/ff/or simple gates also.
xi

HOW TO DESIGN 2D DCT

TELL ME HOW TO DESIGN A 2D DCT CIRCUIT IN IC STUDIO...

8085

specify the two 8085 signals that are used to latch the data in an output port?

CAN

please tell me the code for control area network

BUILT IN SELF TEST FOR RAM

could you please help me in how to find the code for BUILT IN SELF TEST OF RAM in vhdl language please help me

mtcmos

1. how can we increase the threshold voltage of nmos/pmos in MTCMOS?
2. can we use floating gate concept such as adding capacitor to gate of CMOS to increase the threshold voltage of nmos/pmos?

program for digital clock and stopwatch

i need the programs for digital clock and stop watch in microprocessors 8086 trainer kit

programes on 8086 microprocessor

i need various program solutions on 8086 microprocessor

Constarint to the synthesizer

There may arise a situation when tne synthesizer is allowed to selcect either a multiplexer or an and-or gate. How to keep a multiplexer constraint to the synthesizer?

leakage power in submicron technology

help me to find the leakage power of a digital NAND gate in 90nm and 65 nm technology with a HSPICE program .kindly provide the model files for the MOSFETS.Let me know the threshold voltages ,length ,width of nmos and pmos in the 90nm & 65 nm technologies.

RICS processor

1. what is the factor that depends the clock frequency of a RISC processor?
2. how to increase the speed of aRISC processor?

spi slave

want to implement an spi slave block in VHDL and I have the following question:
Do I have to use the CSn (chip select signal) as an asynchronous reset of the SPI slave block?
I don't want to use any additional master clock in order to sample the SPI signals, but I want to use the SCK to clock my flops. So I want to reset the internal FSM every time the CSn is going high.

Is this a good way to implement it?

verilog code

please provide me the verilog code for Path selector in Dual node interconnected SONET/SDH Ring for BLSR.

Number of Process Vs Simulation Time with VHDL

Does more number of processes in a vhdl design file have any effect on simulation time with Modelsim?

zero padding

i m designing an OFDM transceiver in xilinix system generator. i took data and modulated the data using QPSK. then before giving my data to IFFT i need to do its zero padding. my incoming data is at the rate of 800 samples per sec. i want to take 1st 400 samples and store them. i tried to use RAM of depth 400(i dont know i m right or wrong), then next 400 samples in another RAM. and now i want to add 224 zeros in between these two data samples of 400. My data rate has been increases from 800 samples/sec to 1024. How can i store this higher sample rate. and how can i implement my problem in system generator. can i use FIFO any where.

application programs

could u give me some application programs based on 8086 system..
some real time application software.

TRASISTORS

WHY WE R USING TRANSISTORS RATHER THAN USING TRANSFORMER FOR AMPLIFICATION

ANTENNA

WHAT IS THE RADIATION MECHANISM IN SINGLE WIRE

network on chip

i want to know advantages and disadvantages of network on chip over system on chip

Square shape of contact or Via

Why do we have square shape of Via or contact?
someone pl explain?

PCI interface

i need to interface with the PLX, any one is having any reference code or anything,plz provide and guide me.

DIffernce Between VHDL & VERILOG

any one pl tell the differnce between verilog and Vhdl

Help for Code

I am doing a project and in that I need to pause my clock. The module consists of stretch, stop as inputs and clk as output. My module should be able to generate clock signal when stretch and stop are low. When any or both of them are high my clock should stay at 0 position. Can anyone help me with code please.

Loading My Processor Using MIPS ABI

I'm trying to figure out how to load a program written in C++ onto a processor I've designed. The processor uses the MIPS I ISA and I wrote it using Verilator. This being said I have a C++ file that instantiates my processor module as an object.

The C++ file contains 2 arrays, one that represents instruction memory and another that represents data memory. I want to fill the instruction memory array with the instructions in my compiled binary file (made from a simple test program written in C++). To do this I require some knowledge of the MIPS ABI. I have the generic System V ABI and the processor specific MIPS32 ABI documents and I am attempting to determine where exactly in my binary file my program resides.

I need help figuring out exactly what instructions in my binary file I need and how I should use them. Can anyone supply me with some incite as to how I go about sorting through the binary I generated? I know I need the instructions that represent my sample program but what else do I need? The whole set of instructions or just a subset?

Anything will be useful, even redefinitions of my goals if need be.

: ELF Loader

I'm attempting to load segments of an ELF file into a c++ file array. I was told to look into ELF Loaders or libelf. Can anyone tell me what these are and how I can use them to load instructions from a binary file to a C++ file? This will all be used to simulate MIPS I processor.

sin and cosine vhdl code

sin and cosine vhdl code pl

digital watch design

I need verilog code to design a watch and also I want its design blocks

error in accel dsp

n order to convert mat lab code into hdl code I have implemented accel dsp.
but after converting that code one file is missing named "pulse_gen".
just i have used inbuilt fir coding example which is given in the accel dsp example programs.



pl guide me?

vhdl code for floating point multiplier

give a code that will multiply one interger and floating point number so that result will be again in floating point number only.

Xilinx FPGA clock division for UART

I am using a Spartan3 Xilinx FPGA and I want to implement a UART module. The frequency of the crystal on board is 50MHz and I need to divide this frequency.
OK, one way is to implement a counter and use its output as a clock.
But in Spartan3 there are some specific clock generation modules that provides some advantages compared to the counters (clock tree routing, not much skew, phase shift and more..).
From what I saw, these modules cannot divide a clock frequency by more than 16.

Is there some way to use those modules (and not only counters) in order to divide the 50MHz clock with a bigger number (ie 256) and distribute it to the rest circuit?

Transformerless power supply

How can i make transformerless power supply,which produces 24v,18,12,6,and 3v using a capacitor.

megit decoder

vhdl code to design a Meggit Decoder for the cyclic code (7,4) with g(x) = 1 + X + X3 .

IC 7490

explain pin diagram for IC 7490

vhdl code for pn sequence generator

plz give me a vhdl code for pseudo random sequence generator.

8 bit super register

I WANT A VERILOG CODE FOR UNIVERSAL REGISTER
It has 5 inputs: clk, data_in , control, data_sh_r and data_sh_l. The first input, clk, is the clock input where any new operation takes place at the rising edge of this clock signal. The second input, data_in, is an 8 bit input used to load a new data into our register. The third input, control, is a 3 bit input to determine which operation of the eight operations to be performed. The last two inputs, data_sh_r and data_sh_l, each is a 1 bit input used as a shift-in bit when shifting right or left respectively. The Register has two outputs. The first output is 8 bit representing the output data from the register, while the second output is a single bit which is ‘1’ when the output of the register is “00000000” and is ‘0’ otherwise.

code for elevator control....

i need vhdl code for elevator control system

fpga implementation of reed solomon decoder

can anyone send me the vhdl coder using berlekamp massey key equation for decoder for synthesizing and implement on xilinx FPGA with virtex version-4 and series 35 along with explanation....

vhdl code for 8 bit cpu

urgently needed code for 8 bit cpu.PL help.

embedded c

suggest books relating to embedded c (for ARM) IF so send me links

nios based

i am doing the project in the DE2 kit of altera with SD card audio and PS2 keyboard.can anyone help me to make the code to send the input through the keyboard and view the result in LCDmodule

state space model of AC servo motor/PMSM motor

my project is to control the position of AC servo motor by sliding mode control so i want the mathematical model of AC servo/PMSM motor(3-phase) i m facing diffculty while generating the mathematical model actually i want to simulate the model in SIMULINK/MATLAB for that i required the [A][B][C][D] matrix or transfer function if any body already work on the same motor or any link regarding the same kindly send memy project is to control the position of AC servo motor by sliding mode control so i want the mathematical model of AC servo/PMSM motor(3-phase) i m facing diffculty while generating the mathematical model actually i want to simulate the model in SIMULINK/MATLAB for that i required the [A][B][C][D] matrix or transfer function if any body already work on the same motor or any link regarding the same kindly send me

PTM module in (*.pm format)

how to use PTM module card (*.pm format http://www.eas.asu.edu/~ptm/)for HSPICE... Because when i used finfet module card for 32nm ptm i got message pmos1 unfound eventhough i have done many attempt but problem presist( kept same name)

how to use BSIM3v3 for modeling mosfet

Tell me how to use bsim3v3 for modeling, since i have written my own mathematical equation and i wanted to modify bsim model card. how to extract parameter (which tools can be used to modify and extract the parameter? does Hspice or spectre support this )... however i have download bsim4 in c - code....

keypad

what the concept of keypad???vhdl programing...interfacing with FPGA board spartan starter kit board?

what are the symmetric signaling schemes

what are the symmetric signaling schemes,and


ddc-db

mj-sib

mj-db

asf-lc the above terms stands for

which type of adder is having less switching transitions and low power and low area?
and also which type of multiplexer is having the same qualities ?

processor verification

How to verify the processor using specman

How to resimulate a verilog-A simulation?

I have simulated a verilog-A netlist using spectre.
I have the savetime file (*.srf) at 55us.
I want to re-simulate design from 55us to 100us.
While doing so, the verilog A models are giving wrong result.

Can anybody tell me how to re-simulate the design.

guidance program

iwant program in "verilog" to giude amissile ,IF the input of target are none {Module Guidance(trgt_distination,trgt_velocity,angle).
THE MISSLE IS GOING ON{x,y}axis (that mean we used the Laws of linear motion )


(by using fpga )

how to implement vhdl coding on fpga

i am doing booth encoded wallace tree multiplier(32 bit) using VHDL/VERILOG .
but i don't know how to implement vhdl code on fpga board .
i am using SPARTAN 3E KIT (FPGA BOARD).

please send me the steps how to run the coding on fpga board FOR 32 BIT VHDL CODE.

Keypad Scanner & LCD

I am trying to program the FPGA such that it takes inputs from HEX Keypad & show the output on LCD. Ex. pressing 4 5 6 9 8 on Keypad should display 45698 on the lcd.
suggest me the logic or some sample codes in VHDl to guide me through..

Matrix Mutliplication

i am planning to design the matrix multiplication,IF any one have the good material for this plz provide me.

2x1 mux using half adders

I need a circuit for 2x1 mux using half adders

Are real nos in VHDL synthesizable???

how to find the average and variance of 25 complex numbers in VHDL.the complex numbers are generated using matlab.I have 2000 complex nos of which i have to find average and variance taking 25 complex nos at a time.

In VHDL, are real nos not synthesisable??if so how should i convert complex no to STD_LOGIC_VECTOR..
pls help me in this regard...,

network on chip

want to know advantages and disadvantages of network on chip over system on chip

how to set VCS MX environment variables

Pl.tell me how to set environment variables for VCS mX in easy way?

lowpower

i need 8*8 singed tree multiplier architecture

automatic room power control

I m working on automatic room power control. But the LDR sensors are not sensing properly. What can I use instead ? Can i use a seven segment display to display the number of members digitally.

FIRE ALARM

I WANT TO KNOW ABOUT THE WORKING PRINCIPAL OF IC UM66 USED IN FIRE ALARMS

Decoder design 1000 to FFFF

Design decoder to get the output 1000 to FFFF?

APPLICATION SOFTWARE

what is the concept of package in application software?

micro()

Needed the timing diagram for OPCODE FETCH?

gsm picocells

i want some info about gsm picocells

1-does gsm phase 2 support these cells?
2-what is the ip backhual?
3-picocells has its on bsc?
4-is there a hand over in these cells?
5-what is the antenna type which picocells connect to the network trough?
6-transmitting and reciveing equations and any other important equation.
7-limits operation voltage of the cells and curennt.

Keypad Scanner & LCD

I am trying to program the FPGA such that it takes inputs from HEX Keypad & shows the output on LCD. Expressing 4 5 6 9 8 on Keypad, should display 45698 on the lcd. suggest me the logic or some sample codes in VHDl to guide me

confuse

What is the relationship between the drain-to-source resistance rds and the channel length modulation lambda???

Variable as real

i have to find velocity with Quadrature decoded singnal. the equation is
velocity =(60*y)/(36*30), Where y is the count which is an integer variable.when i declare the velocity as "Real" i got compilation error message "non constant real variable cannot synthesize". how can i get fractional values of velocity?

low power consume

1.Which multiplier (array,baugh wooley,booth) consume low power
2.what is the power consumed by these multiplier, pls specify it seperately..

SAFER(Security And Fast Encryption Routine)algrthm

Is there any code for SAFER ALGORITHM in VHDL r in Verilog

about FPGA and ASIC

Need complete information about FPGA and ASIC

32nm CMOS Models

I am conducting research about 32nm CMOS technology and I am searching for the model files that is compatible with Mentor Graphics Tools (Eldo simulator) level 53 or 54.

Drive circuit

What is the value of capacitor used in IRS21853 and how is it being selscted

registergroup

Why registers B,D,H are paired with C,E,L registers respectively? why not any other group?

IEEE standard

help me in writing testbench for IEEE 1149. JTAG,boundary scan standard (Test access port)

cmos and bipolar technology

please help to get the answer of "compare the performance of cmos and biploar technologies",will be very usefull.

fpga and steppermotor

tell me that how many stepper motor can be controlled byfpga spartan ii

7segment

I need to display different numbers on the 7segments that are on the fpga according to the input I have. For example if I want to display the number 250, 2 on the 1st segment, 5 on the 2nd and 0 on the 3rd... How do I do it in VHDL pls?

Till now I am only capable of displaying the same number on all of the segments. My fpga is a spartan 3e-100

If anyone could help me I would really appreciate.

punch through devices

What are punch through devices? What are there advantages? Is there any advantage if we use them as memory devices?

BJT vs. MOSFET gain comparison

for a mosfet in common source configuration
voltage gain A_mos = -gm*(ro||RD||RL)

and for a BJT in common emitter configuration,
A_bjt = -gm*(ro||RC||RL)

where, ro = output resistance = VA/IC or ID, VA=early voltage, IC=bias collector current and gm =transconductance parameter

considering RC=RD and load, RL to be the same, what can be said about the relative values of A_mos and A_bjt. What would be the comparitive relation between the values of gm and ro of both devices in general.?

Current Mirror vs. Current Source

Please explain to me the difference between a normal current source and a current mirror(using Mosfets or BJTs).. What advantage does a current mirror offer over a normal current source. Why cant we directly use the reference current used in current mirrors for biasing or other purposes. is it because of lower output impedance that a Mosfet offers and thus lesser dependence of output current on load..??

Priority resolver in PIC

PL.explain about the principle of priority resolver or an circuit example of priority resolver?

Dflipflop

how to find the next bit when there is given a sequence of bits for a given hardware where the hardware is a four bit d-flipflop asynchronous system

basics of programming in alp

i know nothing abt alp can you help me out...

Generation of .tcf file

suggest me how to generate the .tcf file which is needed for dynamic power analysis in Cadence RTL Compiler tool.

effect

Is there any first order effect in mosfet? Is there any first order effect in mosfet?

7segment

I need to display different numbers on the 7segments that are on the fpga according to the input I have. For example if I want to display the number 250, 2 on the 1st segment, 5 on the 2nd and 0 on the 3rd... How do I do it in VHDL pls? Till now I am only capable of displaying the same number on all of the segments. My fpga is a spartan 3e-100. Anyone Pl help me.

punch through devices

What are punch through devices? What are there advantages? Is there any advantage if we use them as memory devices?

Current Mirror vs. Current Source

Please explain the difference between a normal Current Mirror vs. Current Source or BJTs).. What advantage does a current mirror offer over a normal current source. Why cant we directly use the reference current used in current mirrors for biasing or other purposes. is it because of lower output impedance that a Mosfet offers and thus lesser dependence of output current on load..??

want 1KHz clock frequency from 50KHz. can anybody help me?

want 1KHz clock frequency from 50KHz. can anybody help me?