8-bit sine-wave generator at 10 KHz VHDL

Can anyone show me the complete source code of VHDL of an 8-bit sine-wave generator at 10 KHz?

verilog programs

i need verilog programs for 3 modeling

Verilog code for 8251 USART circuit

Does someone have an either behavioral, or structural description of the 8251 USART circuit in Verilog? I need it for a university-project.

sea

want vhdl code for scalable encryption algorithm

increase in pattern count while ATPG DFT

Can anyone suggest on my ques? 1) I had a netlist I generated pattern say 1000 count ,later I had next version of same netlist but if you see the ET generates 11000 patterns. Can anyone update the reason for increase in teh vector count? only-2 scan clocks 2-scan reset. 1st release say 10000 flops 2nd release say 10050 flops.

increase in pattern count while ATPG

Can anyone suggest on my ques? 1) I had a netlist I generated pattern say 1000 count ,later I had next version of same netlist but if you see the ET generates 11000 patterns. Can anyone update the reason for increase in teh vector count? only-2 scan clocks 2-scan reset. 1st release say 10000 flops 2nd release say 10050 flops.

drawing stick diagram

want to know the basics for drawing stick diagram

solutions for Antenna Theory

Could I get the solutions for Antenna Theory and Design (2nd Ed., Stutzman & Thiele)Please?

How to get into the field of research?

Someone pl, guide me through the process for getting into the field of research in digital electronics.

microwind

i need to know abt MICROWIND software.anyone who knows the same,please help me...

define a matrix in verilog

i want to implement duetcsh jozsa problem of quantum mechanics on fpga so i want to know how we can define a matrix in verilog and how can i multiply two matrix in verilog

electronic voting machine

i am trying to implement an Electronic Voting Machine in vlsi. can anyone plz give me an idea how to start with it or suggest some website where they can give me details about the same. i want my result(no. of votes gained by each candidate) to be displayed on 7 segment of my FPGA board. so can anyone highlight me how to write the code for the same.

prpgram

i want solution for following
program to simulate tossing of die using vector interrupt key and rst7.5
program to add two 8-bit BCD number without using DAA instruction

program

Iwant program
1.8085 program to add two 8 bit data without using accumulator register.
2.To find (n^2)^2 - n is a hexa decimal number

program

I want fibonacii series program with algorithm

www.asic.co.in

I found this new site www.asic.co.in it contains real time interview questions(FPGA, RTL, CMOS,SYNTHESIS) compiled from many design engineer interview experience a must see and read for every VLSI engineer.

report on blue eyes

plz let me know the report on blue eyes

information of microcontroller

how can I started with microcontroller?

basic of microcontroller

i want know about the microcontroller (89c51) basics and its applications.and also its basic troubles when we connect it into the circuit.

many inputs to fpga kit

am working with spartan 3 AN kit.in my project i have 58 inputs. i dont know how to assign this 58 pin in my fpga kit.can i pass my inputs in any other way.

static and dynamic resistance

please explain me about dynamic resistance and static resistance

verilog code for digital calculator

vlsi paper prestation

i like to do paper prestation on vlsi, can u suggest any site to get any old paper. so that i get some idea about that.

use PTM model in hspice

want to use ptm 90nm bulk cmos in hspice, but it has an error "syntax of .lib can not be realized" , help me please.

code for 32 bit floating point ALU

pl. send me the vhdl code for 32 bit floating point ALU(adder,subtractor,multiplier and divider) that follows IEEE754 standard.

LCD interfacing with CPLD

We have VHDL code for LCD display on SPARTAN-3 Kit. Still, we have a probleam of LCD interfacing with CPLD. d

thesis

i m persuing mtech(vlsi) from manit bhopal can anybody suggest me topic for thesis

Wallace tree 32-bit Multiplier VHDL code

I work on my thesis and I want to simulate my theories, but I can not write VHDL code very well. please help on my problem.

verilog code for USB 2.0

need verilog code for protocol of USB 2.0

CMOS

why subthreshold current is there in CMsubOS???

floating point alu in vhdl ineed uagently

....iam doing my project on floating point alu in vhdl...secure arithmetic coding in vhdl...plz send me floating point add,sub,mul i need..

i need floating pt alu

.plz send me floating pt alu vhdl code.

floating point division+vhdl code

iwant vhdl code for floating point division.help me

netbook and vlsi applications

is it possible to run vlsi/fpga/embedded tools/applications in netbook? what about performance,speed on running these programs?

digital energy meter

i need a complete project thesis, hardwarre and software on digital energy meter. any body help me in this regard. thanks

I NEED A MOBILE CIRCUIT DIAGRAMS

ANY HAVE A COMPLETE DIAGRAMS SEEND TO ME PLEASE

verilog code 4 4-bit alu

can anyone give me a 4-bit alu verilog code?

parallel in serial out

please give the parellel in serial out verilog program.

setup and hold tim

Why is the set up and hold time required at all....i mean where is this extratime helped in the circuit..can u explain w.r.t to the cmos structure of the Flip Flop...as in is that some cap requires that or something else which requires that

mobile circuit diagram

I need all type of nokia mobile circiut diagram.

vt of nmos

gate is responsible for the formation of channel.if the gate voltage is greater than vt then channel will form.then why the reason for getting VDD-Vt rather than VDD at the source,as VDD is not responsible for formation of channel.

: 8 point FFT in FPGA

if any body has the code for 8 point FFT for XILINX spartan board

Simulation Types

What are the different types of simulation like functional simulation, timing simulation , ...

8-bit square root

i need to implemant an 8-bit square root code

fpga based alarm door security

i need to design an alarm door security by using vhdl that will embedded on fpga.this security will use keypad that need user to enter the password for security. if the user enter the wrong password for three times,this alarm will be ringing instead of block the door. please help me in designing the source code for programming the ic by using vhdl.

many inputs to fpga kit

i am working with spartan 3 AN kit.in my project i have 58 inputs. i dont know how to assign this 58 pin in my fpga kit.can i pass my inputs in any other way.

fast bus serial or parallel

I'm looking for a way to connect my peripheral chip with main application processors or base band chips (external connection i.e. on board). I don't want to use PHY for serial interconnect. For example, currently I’m using SPI which is fast enough (40 MHz) but I want to be compatible with other fast I/Fs. what protocols do you know that are used by main AP vendors? TI, Broadcom, Qualcom, Samsung, Marvel, etc?

details about clock cycles

kindly explain me about the number of clock cycles needed for division in 8086 processor.

evolution modes of 8085 microprocessor

what are evolution modes and addressing modes of microprocessor

adder

how many multiplexers are required to design a full adder

8 point FFT in FPGA

if any body has the code for 8 point FFT for XILINX spartan board ,please help

declaring an integer in port map

how do i declare an integer using port map? I wish to connect the address lines of my rom module to the address controlling lines of my other module how do i go about this? for example i have an address which is integer range 0 to 5. Is this the proper way to write it?
U1: cntrl_module port map (adress(0)

how to write the code of image in verilog

dont known how to write the code of 512*512 grayscale image in verilog.

Ring Oscillator

have few questions abt RO, I know how it works but: what is it used for, i read that it is used for measuring delay. but delay of what? and how? Please clarify my question.

Keep_hierarchy

What is keep hierarchy in xilinx xst for what purpose it is used?

topics regarding project

i am pursuing m.tech in VLSI and i need a good VLSI project that is based on communication , it can be based on any software but i would prefer CADENCE tool as it is available at my institute. so plz anyone, help me out if you have a solution to my problem.

trafic light conversion

I am trying to convert an old bulb style traffic light to work on house current! 120 volt. Can someone help me?

hardware accelerator detection in xilinx microblaz

similar to impulseC in xilinx-microblaze is there any solution to automatically detect which portions to be converted to hardware accelerator for optimization?

WARNING:Xst:647 - Input is never used.

i dont understand why it showing the particular error; answer with reason? entity rising_edgefuntion is port (clk : in std_logic; a : in std_logic; b : out std_logic); function sathish_falling_edge(signal s: std_logic) return boolean is begin if (s'event) and (s = '0') and (s'last_value= '1') then return true; else return false; end if; end sathish_falling_edge; end rising_edgefuntion; architecture Behavioral of rising_edgefuntion is begin process(clk,a) begin if sathish_falling_edge(clk) then b <= a; end if; end process; end Behavioral;

akhilnair

want ans about internal architecture of 8085

microblaze project

pl suggest a project idea using virtex5 microblaze as part of m.tech(vlsi&es)

why IDDQ and IDDT

can any one tell about iddq and iddt testing

E123 MUX / DEMUX Transceiver IP Core

please frd me to verilog code( which can be synthesized ) or block diagram or any details regarding the below mentioned. The E123MUX is a VLSI core that provides the E13 functions needed to multiplex and demultiplex 16 independent E1 signals to and from an E3 signal that conforms to the ITU-T G.751 Recommendation. The E1 and E3 signal an interface is NRZ only. The E123MUX can also be configured to operate as an E12 or E23 multiplexer and demultiplexer. Sixteen E1 signals can be multiplexed and demultiplexed to and from four E2 signals that conform to the ITU-T G.742 Recommendation. Alternatively, four E2 signals can be multiplexed and demultiplexed to and from one E3 signal. The E2 signal interfaces are also NRZ only. Any 4 lines of 16 E1s can be multiplexed in one E2.The E123MUX uses memory locations for setting control bits and reporting status information. Microprocessor 8-bit bus provides the access of memory locations of E123MUX/DEMUX. Feature Summary: E1 (2048 kbit/s) multiplexer/demultiplexer for ITU-T Recommendations: G.742 (8448 kbit/s E2 frame format) G.751 (34368 kbit/s E3 frame format) Multiplexer/demultiplexer converts: 16 E1s to/from 1 E3 (E13 skip mux), or 16 E1s to/from 4 E2s, or 4 E2s to/from 1 E3 (E12/E23 split mux) Select any 4 E1s to make one E2 through microprocessor interface Generates and detects E2 and E3 alarms Microprocessor input/output 8-bit bus provides split mode Intel interface

dynamics solutions

i am interested in finding the solutions in the 11th edition hibbeler ,in chapter 13 in dynamics

80286, 80386, 80486 Architecture and Pin conf

I just need a complete notes on 80286, 80386, 80486 Architecture and Pin configuration notes.

8086 interfacing with 8237/57

please give me detailed info of 8086 interfacing with 8237/57

4 bit multiplier with shift and add

Can anyone send me a 4 bit multiplier with shift and add method within 12 hour? please...

5 bit sequence detector

i need a vhdl code for 5 bit sequence detector

microprocessor 80286

provide me with a complete informations about 80286 architecture and pin configuration

RTC DS1307 INTERFACING IN VHDL

I AM DESIGNING A DAQ PROJECT. FOR THIS I NEED THE IDEA FOR RTC INTERFACING WITH FPGA IN VHDL? CAN ANYONE SEND ME THE SUGGESTION ?

what is FPGA & ASIC?

i know the functionality of PAL,PLA. but i could't understand the logic blocks of cpld & fpga. Give some details & web address for the same. which book i have to follow? i have some doubts. 1.Is FPGA only for digital ckts? For analog circuit design what we r using? 2.What r the other technologies(like FPGA & ASIC)existing for IC Design(digital & Analog)? 3.What is EDA tools? 4.i need some details that hardware design Engineer must know.

vhdl code for solar tracker

please send vhdl code for solar tracker

size NMOS and PMOS to increase Vt

How do you size NMOS and PMOS transistors to increase the threshold voltage ?

vlsi tecnology

1what is the main difference between fpga and asic 2while simulating the cell in vlsi by using cad tools for vlsi which language is used is it same as vhdl 3 how vhdl and vlsi are interrelated 4 what is the difference between fullcustom and semicustom design

exponential function code in vhdl

want urgently.please explain code in vhdl/verilog

need code for division in 8086

please send me code for 64 by 32 bit diviion in 8086 microprocessor

difference between microprocessor and microcon

please explain in detail the difference between microprocessor and microconroller

Stepper motor datasheet

any one have the datasheets of stepper motor than pls

what is a "timing arc"?

don't know what it is "timing arc" in VLSI. I saw a article. it mentioned a FF has one timing arc. A LATCH has two timing arc. would you explain about "timing arc"?

Cryptography and Network

Please provide the solution manual to Cryptography and Network Security

programs related to logical design

i need all programs related to logical design in verilog

FAN IN & FAN OUT

.i am really cofused with these two words FAN IN & FAN OUT.can anyone explain me these two?

Dalgorthem

iam doing project on D-algorthem,pls help to develop the vhdl code

Need to reconfigure FPGA on NIOS developement kit

Iam having NIOS developement kit Startix edition. When i put on the power supply it goes to preconfigured bit stream is activated.Even after removing flash and eventhough we program the new sof in FPGA.Due to this the LEDs are continuously glowing.could you help me how to burn a standalone RTL on to this board(FPGA)..

Floating Point ALU

how can i generate code for floating point ALU (adder,subtractor & multiplier) in VERILOG? and also give the idea of synthesis report of it.

tell me adout Analog VLSI

help me in understanding Analog VLSI (with the help of example) plzzz give me any EXAMPLE project on it

VHDL Code for floating point multiplication

need VHDL benchmark program of floating point multiplication

microprocessor design

how can i design a microprocessor system using a single memory space for both ROM and RAM and INPUT/OUTPUT ports noting the limitation on the number of input and output ports on 8085A microprocessor reference

ebooks download on vlsi

i want the website for ebooks download on vlsi.plz

crc implementation

1.1 Read the data frame sequence length from the user in a named file (frame is sequence of bits variable from a minimum size to maximum size). The program should read: 1.1.1 the file of pattern of 0 and 1 and 1.1.2 its max. length defined by the length and be stored in file.

need a simple code

can somebody plz give me a code in verilog that converts a 12 bit binary number into a decimal number.

Speed checker for highways

I've a speed checker circuit which is based on timer IC.This circuit mainly consists of two LDR and two leser and seven segment display for showing the counting.That counting will give the speed/hr by using a formula i.e speed=3600/counting.Now my question is ,how can i convert that counting into visual unit.Means that speed should be display by using 7-segment.

8086 microprocessor & assembly language

i need full notes on 8086 microprocessor &assemply language programming.

artificial passenget

want to give a ppt on artificial passenger .please help me.

verilog code of DES encryption

i am in urgent need of DES code in verilog. have made the code but i am not able to do the timing analysis .

alp pgms

get me ans for 1)alp for ascending using 8085 2)architecture &block diagram of keyboard dislay interfacing with 8085 3)alp for largest in array using 8085