Constarint to the synthesizer

There may arise a situation when tne synthesizer is allowed to selcect either a multiplexer or an and-or gate. How to keep a multiplexer constraint to the synthesizer?

leakage power in submicron technology

help me to find the leakage power of a digital NAND gate in 90nm and 65 nm technology with a HSPICE program .kindly provide the model files for the MOSFETS.Let me know the threshold voltages ,length ,width of nmos and pmos in the 90nm & 65 nm technologies.

RICS processor

1. what is the factor that depends the clock frequency of a RISC processor?
2. how to increase the speed of aRISC processor?

spi slave

want to implement an spi slave block in VHDL and I have the following question:
Do I have to use the CSn (chip select signal) as an asynchronous reset of the SPI slave block?
I don't want to use any additional master clock in order to sample the SPI signals, but I want to use the SCK to clock my flops. So I want to reset the internal FSM every time the CSn is going high.

Is this a good way to implement it?

verilog code

please provide me the verilog code for Path selector in Dual node interconnected SONET/SDH Ring for BLSR.

Number of Process Vs Simulation Time with VHDL

Does more number of processes in a vhdl design file have any effect on simulation time with Modelsim?

zero padding

i m designing an OFDM transceiver in xilinix system generator. i took data and modulated the data using QPSK. then before giving my data to IFFT i need to do its zero padding. my incoming data is at the rate of 800 samples per sec. i want to take 1st 400 samples and store them. i tried to use RAM of depth 400(i dont know i m right or wrong), then next 400 samples in another RAM. and now i want to add 224 zeros in between these two data samples of 400. My data rate has been increases from 800 samples/sec to 1024. How can i store this higher sample rate. and how can i implement my problem in system generator. can i use FIFO any where.

application programs

could u give me some application programs based on 8086 system..
some real time application software.

TRASISTORS

WHY WE R USING TRANSISTORS RATHER THAN USING TRANSFORMER FOR AMPLIFICATION

ANTENNA

WHAT IS THE RADIATION MECHANISM IN SINGLE WIRE

network on chip

i want to know advantages and disadvantages of network on chip over system on chip

Square shape of contact or Via

Why do we have square shape of Via or contact?
someone pl explain?

PCI interface

i need to interface with the PLX, any one is having any reference code or anything,plz provide and guide me.

DIffernce Between VHDL & VERILOG

any one pl tell the differnce between verilog and Vhdl

Help for Code

I am doing a project and in that I need to pause my clock. The module consists of stretch, stop as inputs and clk as output. My module should be able to generate clock signal when stretch and stop are low. When any or both of them are high my clock should stay at 0 position. Can anyone help me with code please.

Loading My Processor Using MIPS ABI

I'm trying to figure out how to load a program written in C++ onto a processor I've designed. The processor uses the MIPS I ISA and I wrote it using Verilator. This being said I have a C++ file that instantiates my processor module as an object.

The C++ file contains 2 arrays, one that represents instruction memory and another that represents data memory. I want to fill the instruction memory array with the instructions in my compiled binary file (made from a simple test program written in C++). To do this I require some knowledge of the MIPS ABI. I have the generic System V ABI and the processor specific MIPS32 ABI documents and I am attempting to determine where exactly in my binary file my program resides.

I need help figuring out exactly what instructions in my binary file I need and how I should use them. Can anyone supply me with some incite as to how I go about sorting through the binary I generated? I know I need the instructions that represent my sample program but what else do I need? The whole set of instructions or just a subset?

Anything will be useful, even redefinitions of my goals if need be.

: ELF Loader

I'm attempting to load segments of an ELF file into a c++ file array. I was told to look into ELF Loaders or libelf. Can anyone tell me what these are and how I can use them to load instructions from a binary file to a C++ file? This will all be used to simulate MIPS I processor.

sin and cosine vhdl code

sin and cosine vhdl code pl

digital watch design

I need verilog code to design a watch and also I want its design blocks

error in accel dsp

n order to convert mat lab code into hdl code I have implemented accel dsp.
but after converting that code one file is missing named "pulse_gen".
just i have used inbuilt fir coding example which is given in the accel dsp example programs.



pl guide me?

vhdl code for floating point multiplier

give a code that will multiply one interger and floating point number so that result will be again in floating point number only.

Xilinx FPGA clock division for UART

I am using a Spartan3 Xilinx FPGA and I want to implement a UART module. The frequency of the crystal on board is 50MHz and I need to divide this frequency.
OK, one way is to implement a counter and use its output as a clock.
But in Spartan3 there are some specific clock generation modules that provides some advantages compared to the counters (clock tree routing, not much skew, phase shift and more..).
From what I saw, these modules cannot divide a clock frequency by more than 16.

Is there some way to use those modules (and not only counters) in order to divide the 50MHz clock with a bigger number (ie 256) and distribute it to the rest circuit?

Transformerless power supply

How can i make transformerless power supply,which produces 24v,18,12,6,and 3v using a capacitor.