Biasing Circuit in CMOS

how to implement biasing circuit in CMOS. Does it's structure depends on opamp circuit? Pls explain to me what is the criteria for designing the biasing circuit?

Registring layout design

how can we compare two Integrated circuits layout to stop piracy of layout?

some problems plz help!

my queries! 1.how can we get a 3/2 clock,ie a clock output with high for 1 and a half cycle of input clock and low for one clock cycle of input? 2.why do constant current source made from BJT have high gain? 3.why is offset voltage present in saturated BJT and not in MOSFET? 4.how does putting a source follower as output stage in opamp help in avoiding loss of gain when a low value load resistor is connected to amplifier? 5.in what cases do v need to double clock a signal before presenting to a synchronous state machine? 6.why do v need to put a gate resistance in mosfet circuits? 7.you have a driver that derives a long signal & connects to an input device. at the input device ther is either overshoot,undershoot or signal threshold violations,what can be done to correct this problem?

I2C EEPROM [24C256] INTERFACING WITH FPGA IN

what is FPGA & ASIC?

i know the functionality of PAL,PLA. but i could't understand the logic blocks of cpld & fpga. Give some details & web address for the same. which book i have to follow? i have some doubts. 1.Is FPGA only for digital ckts? For analog circuit design what we r using? 2.What r the other technologies(like FPGA & ASIC)existing for IC Design(digital & Analog)? 3.What is EDA tools? 4.i need some details that hardware design Engineer must be known.

punch through implant

what is punch through implant? how will it affect the threshold voltage?

vhdl code for 8255

i want vhdl code for 8255 i want vhdl code for 8255

how to test a FPGA Look-up Lable ?

"An Optimum ORA BIST for Multiple Fault FPGA Look-Up Table Testing" which is an IEEE 2006 paper can any one guide me how to write the testing code for an FPGA in Verilog HDL.

fifo feature

How to verify fifo(like overflow r empty) feature ....? Can anybody give suggestions i need to verify this in system verilog language

wavelets-verilog program

please help me to write code for image comperession using haar wavelet in verilog

: latest trends in electronics

plz tell me some latest trends in electronics

use of configuration declaration

where we use configuration declaration in vhdl.Please send me the datas about SATRACK.andPPT too.

8086 microprocessor & assembly language

i need full notes on 8086 microprocessor &assemply language programming.

transistor as a switch

Transistor is ON when forward bias and OFF when reverse bias. Based on this property it is acting as a switch. I just want to know that In a IC there are millions of transistor, then how they are making both bias condition for each transistor.

electrodeless lamps

How electrodeless lamps work?

Lift Motion Control

plz send me the program of the Lift Motion Control by Microprocessor....Its urgent.......

vhdl encoder 8 to 3

i need in VHDL code the 8 to 3 encoder (encoder 8:3)...

how to write the code of image in verilog

how can i write the code of 512*512 grayscale image in verilog.

What is difference between 8085 and 8086 ??

The Intel 8085 is an 8 bit microprocessor created in 1977. The Intel 8086 is a 16 bit microprocessor created in 1978. The 8086 was the first chip to start the x86 architecture family. 8085 contains 16-bit address bus and 8-bit data bus 8086 contains 20-bit address bus and 16-bit data bus

final year project ideas

final year project lists availablity in any web site for indian engineering students.

Synthesis .....using Design Compiler

I am trying to synthesize a binary counter. The synthesis tool ( using Design Compiler from Synopsys) is generating counter using a full adder and some flip flops and some combinational logic. It is just a simple binary counter, so it should only use just flip flops and simple AND or OR like gates. I know that it depends on the coding style. Can somebody who have already faced such problem give the solution ?

Synthesis .....using Design Compiler

I am trying to synthesize a binary counter. The synthesis tool ( using Design Compiler from Synopsys) is generating counter using a full adder and some flip flops and some combinational logic. It is just a simple binary counter, so it should only use just flip flops and simple AND or OR like gates. I know that it depends on the coding style. Can somebody who have already faced such problem give the solution ?

How to generate subckt file and device model

i am working on an EDA tool which takes subckt files and device model files of a cell (circuit) in CMOS form as input and characterizes it . Is there any way or tool that take schematic of the circuit as input and give me these files in spice format so that i can characterize it with my tool.?????

How to generate subckt file and device model

i am working on an EDA tool which takes subckt files and device model files of a cell (circuit) in CMOS form as input and characterizes it . Is there any way or tool that take schematic of the circuit as input and give me these files in spice format so that i can characterize it with my tool.?????

Microprocessor Assingment BCA-3SEM

Write a program to convert a 2-digit BCD number into hexadecimal.

Could u let me know the working of IC UM66, its pin diagram, and working of IR MUSIC TRANSMITTER AND RECEIVER using IC UM66....

Could u let me know the working of IC UM66, its pin diagram, and working of IR MUSIC TRANSMITTER AND RECEIVER using IC UM66....

IR MUSIC TRANSMITTER AND RECEIVER

Could u let me know the working of IC UM66, its pin diagram, and working of IR MUSIC TRANSMITTER AND RECEIVER using IC UM66....

Lift Motion Control

send me the program of the Lift Motion Control by Microprocessor

HELP ME IN NEED OF PAPERS ON VLSI NEW DEVICE

I REALLY DONT KNOW WHERE TO GET THE INFO BASED ON VLSI .PLEASE HELP ME OUT.

read .csv file in to verilog file

pl. read .csv file in to verilog file

Celtic Noise report

can anyone get me seltic Noise report, uploaded.

Significance of Global skew

tell me significance of Global skew

verilog tutorial

Best tutorial for verilog tutorial
verilog tutorial made for all.
what engineering students require from it
what professional require from it http://vlsiforum.brinkster.net
Needs feed back what they need from verilog tutorialhttp://projectfeedback.brinkster.net
extensive workout result good verilog tutorial for you

VHDL code for Reed Solomon encoder and decoder

need VHDL code for RS(7,3),VHDL code for RS encoder too. can anyone help in this regard

89c51 ic

plz give me information abt 89c51 ic and it's application

cts spec generation

what are the mandatory inputs needed to generate clock tree specification file with encounter and how to generate clock tree spec file for perticular design

vhdl source code required

i need vhdl code for the following titles........ plz do this help, i need urgently, at the maximum those who know any 1 frm this also, plz send the source code....
1.FPGA-based UDP/IP stacks parallelism for embedded Ethernet connectivity 2.Design and Implementation of CDMA based Communication System in FPGA 3.UART Module for Real Time Application 4.Design and Implementation of 8051 Microcontroller in FPGA 5.Design and Implementation of PIC Microcontroller in FPGA 6.Design and Implementation of RISC Microcontroller in FPGA 7.Design and Verification of Inter IC (I2C) bus controller 8.Speed and Direction control of Stepper Motor Using FPGA 9.Design a Low Power 16-bit Booth Multiplier in FPGA 10.Improving Area Efficiency of FIR Filters Implemented Using Distributed Arithmetic 11.Design a High Speed First-in First-out (FIFO) in FPGA 12.Digital Design of DS-CDMA Transmitter and Receiver Using VHDL and FPGA 13.Design and Implementation of RSA Algorithm on FPGA 14.Design and Implementation of 8085 Microprocessor in FPGA

Please correct my KeyBoard Interface code

I am interfacing the keyboard with LCD on spartan-3e kit every thing is going well but when i dump the code on the kit to check it i am facing a problem: The problem is when i am typing the keyboard(KB) characters each and every character is getting displayed but on the same address that is, when i press A on KeyBoard it is displayed on the 00(1st) location on the LCD screen & later when i press B it is also displayed on the same 00(1st) location on the LCD screen by overwrighting A (but it must be displayed next to A).Can any one please fix my code

Code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity KB_2 is Port ( FPGAclk,rst : in STD_LOGIC; Lcd_on : in STD_LOGIC; KB_Clk : inout STD_LOGIC; KB_Data : inout STD_LOGIC; sf_ce0 : out STD_LOGIC; rs : out STD_LOGIC; rw : out STD_LOGIC; en : out STD_LOGIC; q_LED : out STD_LOGIC_VECTOR (7 downto 0); q : out STD_LOGIC_VECTOR (3 downto 0)); end KB_2; architecture KB_2 of KB_2 is --********************************************************************************-- --**************************KEY BOARD SIGNAL DECLARATION**************************-- --********************************************************************************-- signal KBD_Temp : STD_LOGIC_VECTOR (7 downto 0):="00000000"; signal KBD_Temp2 : STD_LOGIC_VECTOR (7 downto 0):="00000000"; signal count_KB : INTEGER range 0 to 43; --********************************************************************************-- --**************************LCD SIGNAL DECLARATION********************************-- --********************************************************************************-- signal lcd_temp : STD_LOGIC_VECTOR (5 downto 0); signal lcd_stuff : STD_LOGIC_VECTOR (6 downto 0) := "0000000" ; signal lcd_count : STD_LOGIC_VECTOR (26 downto 0):= "000000000000000000000000000"; signal lcd_en : STD_LOGIC := '0' ; signal b : STD_LOGIC := '1' ; begin --**********************************************************************************-- --****************************Scan Code Detection Process*************************-- --**********************************************************************************-- Process Begin wait until KB_Clk='0' and KB_Clk'event; count_KB <= count_KB+1; if (count_KB >= 1 and count_KB < count_kb ="10)" fpgaclk="'1'">KBD_Temp2<=X"41"; --A when X"32"=>KBD_Temp2<=X"42"; --B when X"21"=>KBD_Temp2<=X"43"; --C when X"23"=>KBD_Temp2<=X"44"; --D when X"24"=>KBD_Temp2<=X"45"; --E when X"2B"=>KBD_Temp2<=X"46"; --F when X"34"=>KBD_Temp2<=X"47"; --G when X"33"=>KBD_Temp2<=X"48"; --H when X"43"=>KBD_Temp2<=X"49"; --I when X"3B"=>KBD_Temp2<=X"4A"; --J when X"42"=>KBD_Temp2<=X"4B"; --K when X"4B"=>KBD_Temp2<=X"4C"; --L when X"3A"=>KBD_Temp2<=X"4D"; --M when X"31"=>KBD_Temp2<=X"4E"; --N when X"44"=>KBD_Temp2<=X"4F"; --O when X"4D"=>KBD_Temp2<=X"50"; --P when X"15"=>KBD_Temp2<=X"51"; --Q when X"2D"=>KBD_Temp2<=X"52"; --R when X"1B"=>KBD_Temp2<=X"53"; --S when X"2C"=>KBD_Temp2<=X"54"; --T when X"3C"=>KBD_Temp2<=X"55"; --U when X"2A"=>KBD_Temp2<=X"56"; --V when X"1D"=>KBD_Temp2<=X"57"; --W when X"22"=>KBD_Temp2<=X"58"; --X when X"35"=>KBD_Temp2<=X"59"; --Y when X"1A"=>KBD_Temp2<=X"5A"; --Z when X"0E"=>KBD_Temp2<=X"60"; --` when X"16"=>KBD_Temp2<=X"31"; --1 when X"1E"=>KBD_Temp2<=X"32"; --2 when X"26"=>KBD_Temp2<=X"33"; --3 when X"25"=>KBD_Temp2<=X"34"; --4 when X"2E"=>KBD_Temp2<=X"35"; --5 when X"36"=>KBD_Temp2<=X"36"; --6 when X"3D"=>KBD_Temp2<=X"37"; --7 when X"3E"=>KBD_Temp2<=X"38"; --8 when X"46"=>KBD_Temp2<=X"39"; --9 when X"45"=>KBD_Temp2<=X"30"; --0 when X"55"=>KBD_Temp2<=X"3D"; --= when X"4E"=>KBD_Temp2<=X"2D"; --- when X"54"=>KBD_Temp2<=X"5B"; --[ when X"5B"=>KBD_Temp2<=X"5D"; --] when X"4C"=>KBD_Temp2<=X"3B"; --; when X"52"=>KBD_Temp2<=X"27"; --' when X"41"=>KBD_Temp2<=X"2C"; --, when X"49"=>KBD_Temp2<=X"2E"; --. when X"4A"=>KBD_Temp2<=X"2F"; --/ when X"29"=>KBD_Temp2<=X"20"; --space when others=>null; end case; q_LED <= KBD_Temp2; end if; end process; --********************************************************************************-- --++++++++++++++++++++++++++LCD Initialisation Process++++++++++++++++++++++++++++-- --********************************************************************************-- process begin wait until FPGAclk ='1' and FPGAclk'event; lcd_count <=lcd_count + "0000000000000000000000001"; sf_ce0 <= '1'; case lcd_count(24 downto 18) is --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- --*************************LCD Commands for Initialisation************************-- --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- when "0000000" => lcd_temp <= "000011";--3 when "0000001" => lcd_temp <= "000011";--3 when "0000010" => lcd_temp <= "000011";--3 when "0000011" => lcd_temp <= "000010";--2 when "0000100" => lcd_temp <= "000010"; when "0000101" => lcd_temp <= "001000";--28 when "0000110" => lcd_temp <= "000000"; when "0000111" => lcd_temp <= "000110";--06 when "0001000" => lcd_temp <= "000000"; when "0001001" => lcd_temp <= "001100";--0c when "0001010" => lcd_temp <= "000000"; when "0001011" => lcd_temp <= "000001";--01 when "0001100" => lcd_temp <= "001000"; when "0001101" => lcd_temp <= "000000";--80 1st line addr when "0001110" => lcd_temp <= "000000"; when "0001111" => lcd_temp <= "001100";--return cursor home --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- --*************************Sending Data To LCD************************************-- --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- when "0011000" => lcd_temp(5 downto 4) <= "10"; lcd_temp(3 downto 0) <=KBD_Temp2(7 downto 4); when "0011001" => lcd_temp(5 downto 4) <= "10"; lcd_temp(3 downto 0) <=KBD_Temp2(3 downto 0); when "0011010" => lcd_temp(5 downto 4) <= "10"; lcd_temp(3 downto 0) <="0010"; when "0011011" => lcd_temp(5 downto 4) <= "10"; lcd_temp(3 downto 0) <="0000"; -- space when "0011100" => lcd_temp(5 downto 4) <= "10"; lcd_temp(3 downto 0) <="0010"; when "0011101" => lcd_temp(5 downto 4) <= "10"; lcd_temp(3 downto 0) <="0000"; -- space when others =>lcd_temp <= "010000"; end case; --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- --*************************LCD enable pin operation & assigning data to output****-- --++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++-- b<= lcd_count(17) or lcd_count(16); lcd_en <= b and not lcd_temp(4);--lcd enable pin process lcd_stuff(6) <= lcd_en; lcd_stuff(5 downto 0) <= lcd_temp; (en,rs,rw,q(3),q(2),q(1),q(0)) <= lcd_stuff; end process; end KB_2;

verilog code contest http://vlsiforum.brinkster.net

http://vlsiforum.brinkster.net
VERILOG code contest
very competitive have fun
graduate engineer studying should follow it .learn and skill to become expert and reach to any MNC.

VHDL code contest http://vlsiforum.brinkster.net

http://vlsiforum.brinkster.net
VHDL code contest
very competitive have fun
graduate engineer studying should follow it .learn and skill to become expert and reach to any MNC.

DRINKING WATER ALARM

want to know a detail about DRINKING WATER ALARM circuit describtion

DSP the application of convolution code

primitative with datastructures

what is primitative with datastructures ?

object detecting sensor

Is there any sensor which can detect any object placed anywhere within that sensor range?

Answer of fulladder

Advantages of full adder i want to know.

different types of adders

different types of adders

VHDL code for Reed Solomon encoder and decoder

need VHDL code for RS(7,3)can anyone help in this regard?

applications of vlsi

what are the basic applications of vlsi technology

Reed solomon(255,239) encoder in VHDL code

looking for a rs encoder code in VHDL. i dont want to use ISE cores. can anyone help

8 8-bit ALU register

The task is to design a component which could be used in the core of a microprocessor:
We shall call this Register_ALU: • the design will contain 8 8-bit registers which can be loaded from an external input; • the design will contain a block of logic which will have two 8-bit inputs A[7..0] and B[7..0], and will produce one 8-bit output C[7..0]; • the output will be formed as o A and B, or o A or B, or o A plus B, or o A minus B; • the operation {logical and, logical or, arithmetic plus, arithmetic minus} will be selected by an external input to the design, called Op_Code[1..0]; • the output C[7..0] can be o loaded back into one of the eight internal registers, or o read externally.
please send me the code for this problem

super buffer with interconnects

want to do my thesis in super buffer with interconnects using EDA tools,and the technology to be used is below 180 nm. please guide me.

size NMOS and PMOS to increase Vt

How do we size NMOS and PMOS transistors to increase the threshold voltage

I2C protocol implementation in verilog & VHDL

required I2C protocol implementation in verilog & VHDL. first preference is verilog. vhdl will also do.

Scaling models formulated by Dennard

tell link sites and textbooks where I can find a detailed explanation of the scaling models formulated by Dennard

differential to single ended converter

explain me about the D2S structure i.e,differential to single ended ckt..

computer networking

what is difference between tcp and ip?

output impedence of cs amplifier

how to calculate the output impedence of a cs amplifier using pspice ??? i have some idea but I just need to check whether its right so can anyone please guide??

output impedence of cs amplifier

how to calculate the output impedence of a cs amplifier using pspice ??? i have some idea but I just need to check whether its right so can anyone please guide??

output impedence of cs amplifier

how to calculate the output impedence of a cs amplifier using pspice ??? i have some idea but I just need to check whether its right so can anyone please guide??

copper bonding technology

what is copper bonding technology ?

cadence virtuso -spectre simulator

. i am using for design cadence virtuso,( schematic design),for simulating i am using spectere, can you tell me how to give pulse either 0 or 1 directly irrespective of pulse wave forms.

Related with memory

Please send me detail about different type of memory,there types,how to implement any dynamic memory using verilog code for dump in the FPGA.

iam using spartan II fpga kit.i have to give hall sensor output(nothing but a square pulses) to the fpga input ports.so what is the max i/p value(i.e square pulse voltage 2 volts or 3 volts) i can give to the kit with out damaging i/p ports.

iam using spartan II fpga kit.i have to give hall sensor output(nothing but a square pulses) to the fpga input ports.so what is the max i/p value(i.e square pulse voltage 2 volts or 3 volts) i can give to the kit with out damaging i/p ports.

How to download VHDL code into FPGA

I had a problem downloading my VHDL code to FPGA. I did my simulation with my VHDL code.Now i need to download it into FPGA and display the output on 7segment display.I understand that in order to download, i need to create a new top level entity(port SW1,CLK,LED7SEG) and not using my previous top level entity with 2inputs and 1output(simulation).Only after that i can do my pin assignment,rite?Can anyone provide me with a new top level entity(built in with 7segment decoder code) example?

fpga code of dmb-th transmitter for sail

I developed dmb-th (chinese standard of DVB) tranditter with xilinx's fpga,and fpga code is for sail

diff b/w virtual memory n cache memory

What s the diff between a virtual memory and cache memory?

Sending to/receiving data from USB port

I've been trying to write a simple program in C/C++ under WinXp with VC++ 8.0 that allows me to send to/receive data from to the usb port, so that I can be able to control a digital device. If one of you has an idea about how to do it or knows a certain sorce of material about it, please help me.

Regarding selecting my major ANALOG or DIGITAL DEG

I am doing my MS in vlsi and i have to select my major this fall.i am confused between analog and digital design.please suggest which one has more scope from the job point of view.And i have no particular inclination towards any of these. i am good at both but now i have to select one, only thing is that analog is bit more sifficult than digital in my univ but dats not the point. i am just looking for the one which can fetch me more calls. please suggest me in this coz i knw u guys knw more than i knw.

transmission gate in cmos design

I am working on a design where I needed to isolate two different circuits.I was suggested to use transmission gate but,the transmission gate is leaking the voltage even when it is off.Can anyone suggest me the ideal isolator by either customizing the transmission gate or completely different circuit.

JK flip flop gate level verilog code

can someone give me a gate level or RTL verilog code for JK flip flop? my outputs are always x.

JK flip flop gate level verilog code

can someone give me a gate level or RTL verilog code for JK flip flop? my outputs are always x.

application of 8086?

what is the application of 8086?

GSRC floorplan benchmark suite ?

can i get GSRCbenchmark suite n100, n200, and n300?

Is Generate statement is Synthasizable

I tried to get the resource utilisation of a given design. I have instantiate the component number of times with generate statement.then i done the synthesis in xilinx tool but i got the final report mentioned bellow.So please give me the solution to get the utilization of slices.
Selected Device : 2v40cs144-6 Number of Slices: 0 out of 256 0% Number of IOs: 18 Number of bonded IOBs: 18 out of 88 20% -------------------------------------------------------------------------------------- Design: library IEEE; use IEEE.std_logic_1164.all; entity systolic_algorithm is generic ( DATA_WIDTH : integer := 8 ); Port( clk : in std_logic; en : in std_logic; din : in std_logic_vector(DATA_WIDTH-1 downto 0); dout : out std_logic_vector(DATA_WIDTH-1 downto 0) ); end systolic_algorithm; architecture Behavioral of systolic_algorithm is component systolic_pe is generic ( DATA_WIDTH : integer := 8 ); Port( clk : in std_logic; en : in std_logic; din : in std_logic_vector(DATA_WIDTH-1 downto 0); dout : out std_logic_vector(DATA_WIDTH-1 downto 0) ); end component; constant N : integer := 3; type locsignal_type is array(N-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0); signal locsignal : locsignal_type; begin u0: for i in 0 to N-1 generate u10: if (i = 0) generate u11: systolic_pe port map( clk => clk, en => en, din => din, dout=> locsignal(0)); end generate u10; u20: if ((i > 0) and (i < clk =""> clk, en => en, din => locsignal(i-1), dout=> locsignal(i)); end generate u20; u30: if (i = N-1) generate u33: systolic_pe port map( clk => clk, en => en, din => locsignal(i), dout=> dout); end generate u30; end generate u0; end Behavioral;

architecture and pin configuration of 80386

architecture and pin configuration of 80386 microprocessor

regarding antenna radiation

want to ask you in details about radiation mechanism of a)single wire b)two wire c)dipoles d)current distribution on a thin wire antenna

vhdl code for modified booth multiplier

needed vhdl code for modified booth multiplier

block statement

i have written a code with block statement. when i run this statement it shows some error

multiplying two matrix in verilog with the help of

how can i write a program in verilog by which i can multiply 3*3 matrix to another 3*3 matrix . plz send me a simple program how can i define a matrix using array plz tell me how can i creat a 2 d array in verilog

cadence virtuso -spectre simulator

Hi dear users im srinivas. i am using for design cadence virtuso,( schematic design),for simulating i am using spectere, can you tell me how to give pulse either 0 or 1 directly irrespective of pulse wave forms. please send me any idea

Could u let me know the working , circuit description and application of IR music transmitter and receiver using ICum66 in detail.

COMPUTER SYSTEM

3 ques. 1> difference between computer archtecture and organization, 2>what is vlsi system? 3>CPI, MIPS and the relation between CPI & MIPS.

masm pgms

program to make pascal's triangle if anybody knws it plz send me

Asking for the circute diagram of w200 sonyericson

send the circuite diagram of sonyericson W200 model ,

cdma coding

cdma coding in which we use the tata cdma in rim handset or any other cdma handset.

object detecting sensor

Is there any sensor which can detect any object placed anywhere within that sensor range? please send me the link of website where i can get the knowledge regarding that sensor.

Process sequence for fabricating Poly Gate

I am wondering the "correct" sequence for fabricating a layer of gate oxide and poly gate on a bare silicon substrate. The substrate is also implanted with boron. So this is my thinking: bare silicon substrate -> coated with photoresist -> selectively exposed -> exposed region implanted with boron -> then strip the unexposed photoresist. At this point, I am confused on how to proceed to build the layer of gate oxide on which the poly gate is directly built. I will appreciate guidance on how to proceed to build the structure further.

0.35 um Technology Design Guide

I am working on 0.35 um Technology Design Rules. Can anyone pls forward me such document which may help me in constructing so.

define a matrix in verilog

want to implement duetcsh jozsa problem of quantum mechanics on fpga so i want to know how we can define a matrix in verilog and how can i multiply two matrix in verilog

simple 16 bit processor code in vhdl

hi everyone need to simple 16 bit the processor tails in vhdl. please help me

SDRAM PROBLEM

Hi I am using Kingston 512MB SDRAM for my XUP virtex 2 pro development board. I am working on image filtering where I have to transfer the image file to the SDRAM and then filter it by bring the data to the BRAM's. I am struck off into following steps: 1. How can I send a whole image file to the SDRAM. I can put some data on the SDRAM using the EDK C code which is as follows #define XPS_MEM_RAM 0x60000000 // this was the starting address of the SDRAM as //provided by the EDK when I added it to my system Xuint32 *RAM; RAM=XPS_MEM_RAM; RAM[i]=0x12345678; but how to send a full file... Also I am not sure whether the procedure i followed is completely correct??? 2.How can i bring my data(which is in SDRAM) to the BRAM. Can i add BRAM to my EDK system as i added SDRAM... If so how??? I also tried to access the SDRAM with VHDL code but it was quiet complicated. I also heard about SDRAM controller but didn't found any for my SDRAM. Please suggest me something for any of the two problems.

Modelling Transmission Lines

Modelling Transmission Lines

SystemVerilog

Iam working on systemverilog verification since m beginner facing difficulty in running test and writing testbench if anybody have some material r books on systemverilog