Is Generate statement is Synthasizable

I tried to get the resource utilisation of a given design. I have instantiate the component number of times with generate statement.then i done the synthesis in xilinx tool but i got the final report mentioned bellow.So please give me the solution to get the utilization of slices.
Selected Device : 2v40cs144-6 Number of Slices: 0 out of 256 0% Number of IOs: 18 Number of bonded IOBs: 18 out of 88 20% -------------------------------------------------------------------------------------- Design: library IEEE; use IEEE.std_logic_1164.all; entity systolic_algorithm is generic ( DATA_WIDTH : integer := 8 ); Port( clk : in std_logic; en : in std_logic; din : in std_logic_vector(DATA_WIDTH-1 downto 0); dout : out std_logic_vector(DATA_WIDTH-1 downto 0) ); end systolic_algorithm; architecture Behavioral of systolic_algorithm is component systolic_pe is generic ( DATA_WIDTH : integer := 8 ); Port( clk : in std_logic; en : in std_logic; din : in std_logic_vector(DATA_WIDTH-1 downto 0); dout : out std_logic_vector(DATA_WIDTH-1 downto 0) ); end component; constant N : integer := 3; type locsignal_type is array(N-1 downto 0) of std_logic_vector(DATA_WIDTH-1 downto 0); signal locsignal : locsignal_type; begin u0: for i in 0 to N-1 generate u10: if (i = 0) generate u11: systolic_pe port map( clk => clk, en => en, din => din, dout=> locsignal(0)); end generate u10; u20: if ((i > 0) and (i < clk =""> clk, en => en, din => locsignal(i-1), dout=> locsignal(i)); end generate u20; u30: if (i = N-1) generate u33: systolic_pe port map( clk => clk, en => en, din => locsignal(i), dout=> dout); end generate u30; end generate u0; end Behavioral;