E123 MUX / DEMUX Transceiver IP Core

please frd me to verilog code( which can be synthesized ) or block diagram or any details regarding the below mentioned. The E123MUX is a VLSI core that provides the E13 functions needed to multiplex and demultiplex 16 independent E1 signals to and from an E3 signal that conforms to the ITU-T G.751 Recommendation. The E1 and E3 signal an interface is NRZ only. The E123MUX can also be configured to operate as an E12 or E23 multiplexer and demultiplexer. Sixteen E1 signals can be multiplexed and demultiplexed to and from four E2 signals that conform to the ITU-T G.742 Recommendation. Alternatively, four E2 signals can be multiplexed and demultiplexed to and from one E3 signal. The E2 signal interfaces are also NRZ only. Any 4 lines of 16 E1s can be multiplexed in one E2.The E123MUX uses memory locations for setting control bits and reporting status information. Microprocessor 8-bit bus provides the access of memory locations of E123MUX/DEMUX. Feature Summary: E1 (2048 kbit/s) multiplexer/demultiplexer for ITU-T Recommendations: G.742 (8448 kbit/s E2 frame format) G.751 (34368 kbit/s E3 frame format) Multiplexer/demultiplexer converts: 16 E1s to/from 1 E3 (E13 skip mux), or 16 E1s to/from 4 E2s, or 4 E2s to/from 1 E3 (E12/E23 split mux) Select any 4 E1s to make one E2 through microprocessor interface Generates and detects E2 and E3 alarms Microprocessor input/output 8-bit bus provides split mode Intel interface