Regarding schmoo plots

What are schmoo plots?

Liao wong algorithm

which edges are to be considered as forward path and feedback path in a given graph for calculating longest path using liao wong algorithm.pl explain about ordering in binary decision diagrams ?

mcu or mp

even the mcu has the more advantage than the mp y don we use the mcu instead of mp in our pcs and labtops????

Losses of Bytes in TEMAC transmitting

We are targetting Spartan6 device.package is LX45.we want to transmit data through ethernet.But we are lossing bytes during transmitting.We are using IPCORE.Can any one guess the reason?

FELICS ALGORITHM

doing project in loss less image compression using VLSI oriented FELICS Algorithm help me to write code in Verilog.i need some ideas to implement

7490 counter

how to use 7490 counter and the internal architecture

code for a transfer function

i want the vhdl code for a two zeros two pole transfer function

FIFO Depth Means wat.?

If i get the FIFO depth as 2, then wat exactly it means....

single wire radiation

how radiation is achieved?

vhdl code to interface fpga with lcd

pl tell me the steps to be followed while coding or posting the code for interfacing a virtex II pro fpga with lampex lm16200 lcd.

PRBS checker module in Verilog

how to code for a prbs checker and error injector module in verilog

Reconvergence

what recnvergence mean in eda

ihld

needed timingdigram of ihld

cmos design challenges in the Nanotechnology era

please give me breaf description about cmos design challenges in nanotechnology era

fpga,asic

please give me the details fpga design in bus interface i.e:1553

BUBBLE

how to sort using 8086 micro proccessor

how to view layout in cadence virtuoso with lef?

I have LEF, DEF, LIB, PLIB, DB, etc. all files from SoC and such but no gds. These files are from ARM with general I/O and pad cell but I need to see them with virtuoso. One person told me maybe a synopsys function called fdi2gds on the lef file, but I'm not sure how to use it.

operating frequency of VLSI

what is the operating frequency of VLSI?

Timing constraints in XILINX ISE

pl explain me about timing constraints in xilinx ISE.
exactly wat am looking is how to apply timing constraints.
if possible explain brief description for counter/ff/or simple gates also.
xi

HOW TO DESIGN 2D DCT

TELL ME HOW TO DESIGN A 2D DCT CIRCUIT IN IC STUDIO...

8085

specify the two 8085 signals that are used to latch the data in an output port?

CAN

please tell me the code for control area network

BUILT IN SELF TEST FOR RAM

could you please help me in how to find the code for BUILT IN SELF TEST OF RAM in vhdl language please help me

mtcmos

1. how can we increase the threshold voltage of nmos/pmos in MTCMOS?
2. can we use floating gate concept such as adding capacitor to gate of CMOS to increase the threshold voltage of nmos/pmos?

program for digital clock and stopwatch

i need the programs for digital clock and stop watch in microprocessors 8086 trainer kit

programes on 8086 microprocessor

i need various program solutions on 8086 microprocessor