Voltage Source & capacitor, Voltage source & Diode

what will be the Output voltage when a Capacitor is connected to a voltage source in series. The circuit is not closed Figure ----------. Vin vout1 ____________. Similarly instead of a capacitor if a diode is connected what will be the output ------ -> ----. Vin vout2 ______________. ------ <- ----. Vin vout3 ->,<- are diodes ______________.

Embedded Systems

in future the growth and offers in embedded..

vhdl for nco(DDS)

urgently required a dds signal genarator vhdl description to implement it on spartan3 xilinx fpga using xilinx 8.2.I want all the files needed to implement it.And How can I use lpm components(or instead of them) like lpm rom,lpm ff,lpm add sub in xilinx ise8.2?

VHDL code for CIC Decimation

I need a general code for vhdl cic decimator for factor 5. My Fs is 400Mhz and IF is 5Mhz.

cts spec generation

what are the mandatory inputs needed to generate clock tree specification file with encounter and how to generate clock tree spec file for perticular design

need guidence to give connstraints

need to learn to give constraints to a verilog model using xylinx sparten 2 xst200 pq208

need guidence to give connstraints

need to learn to give constraints to a verilog model using xylinx sparten 2 xst200 pq208

FINAL YEAR PROJECTS IDEAS

PROJECTS for BE,MCA,electronics,communication get an idea let us discuss to prepare well on this such a vast topics to prepare well for PROJECT work.Do some good job to become industry ready in real.

any one have MSK source code

really need the msk vhdl source code..pls help

need matlab code or vhdl code

want to write the matlab and vhdl code for convolution of samples of input signal of 5Mhz wave and the filter coefficients of Fir filter. my task goes like this my sampling frequency is 400Mhz for filter so i have to reduce to 20Mhz. so i have to decimate it by 20(5x2x2) then i will obtain the 20Mhz. i need the sampling frequency of 20Mhz so i need to downsample and decimate so i need a matlab code and vhdl code for the following (any code will be useful for me) i am using cic decimation with 5 for first stage and then compensating with Halfband Filter and decimate by 2 and then FIR eqiripple filter with decimation of 2 then i will get 20Mhz the new sampling frequncy the input 5Mhz will convolute with cic filter the output of the conv signal will convolute with halfband filter coeff the output of the halfband will conv with fir eqiripple filter coeff then i need the final result with 20Mhz but as CIC doesnt generate any filter coefficents how we will conv the input signal with the cic filter. parameters: my pass band is 10Mhz , stop band is 15Mhz and pass band attuenation of 0.1dB and stop band attuenation of 30dB for the final FIR filter the output of the conv signal will convolute with halfband filter coeff the output of the halfband will conv with fir eqiripple filter coeff then i need the final result with 20Mhz but as CIC doesnt generate any filter coefficents how we will conv the input signal with the cic filter. parameters: my pass band is 10Mhz , stop band is 15Mhz and pass band attuenation of 0.1dB and stop band attuenation of 30dB for the final FIR filter

IR music transmitter and receiver using IC um66

Could u let me know the working , circuit description and application of IR music transmitter and receiver using ICum66 in detail.

Verilog code for 8251 USART circuit

Hi! Does someone have an either behavioral, or structural description of the 8251 USART circuit in Verilog? I need it for a university-project.

layer mapping

does any one knows how to map the layers while migrating from one technology to another.

edge effects

what is meant by "edge effects" in short channel MOSFETs?

MSK VHDL coding

i really need the minimum shift keying modulation source code

FINAL YEAR PROJECT USING VERILOG CODE

FINAL YEAR PROJECT USING VERILOG CODE NEED SOME IDEA THAT DOING BE FINAL YEAR PROJECT USING VERILOG CODE CAN EXCELL TO BECOME INDUSTRY READY.

FINAL YEAR PROJECT USING VHDL CODE

FINAL YEAR CODE USING VHDL CODE.NEED SOME IDEA WHERE CAN BE EXCELLED USING VHDL CODE TO BECOME INDUSTRY READY.DOING BE FINAL YEAR PROJECT

FINAL YEAR PROJECT

FINAL YEAR BE project

RS 232 Communication Problem

I've built a RS232 receiver and transmitter.. I've tested it by sending some 64 bit data(multiplexed as 8 bits) through TxD and routing it back to RxD and read is using same monitoring software through which I've sent the data.. The problem is I'm getting a continuous loop of data, that too only the last symbol(last 8 bits of the multiplexed data)..... I want only the 64 bits to be displayed.... The symbol need to be sent only once... What should I do??

: Second order effects in MOSFETs

Different textbooks give different opinions about second order effects of MOS characteristics. Please explain in simple words,what is meant by the second order effects and how they affect the working of a MOSFET.

verilog code for 16 bit alu with memory

verilog code for a 16 bit alu with memory is required

BLUE EYE

WOULD LIKE GIVE PAPER PRESENTATION ON BLUE EYES TECHNOLOGY.PLEASE SEND ME WHOLE INFORMATION ABOUT IT .PLEASE.

connection of stepper motor lcd display

how to connect stepper motor and lcd dispay with 89c51 atmel microcontroller

ieee 802.3 frame format

iam doing project on frame synchronization..concept...in that iam implementing ieee802.3 frame format... can any one help in writting vhdl code and verilog code for the ieee802.3 frame format.. frame contain 1.preamble ..56 bits of 10......10..10 format. 2.start frame delimiter 1 byte..10101011.. bits.. 3.length.type field 4.data field 5.padding field 6.frame check sequence can any one help in writting the code foe this modules

I2C EEPROM [24C256] INTERFACING WITH FPGA IN

I AM DESIGNING DAQ PROJECT IN CYCLONE II FPGA. CAN ANYONE TELL ME THE PROCEDURE FOR INTERFACING TEH ATMEL SERIAL EEPROM AT24C256 WITH FPGA IN VHDL CODE? AWAITING FOR YOUR RESPONSE.

RTC DS1307 INTERFACING IN VHDL

AM DESIGNING A DAQ PROJECT. FOR THIS I NEED THE IDEA FOR RTC INTERFACING WITH FPGA IN VHDL? CAN ANYONE SEND ME THE SUGGESTION ? AWAITING FOR YOUR RESPONSE.

Model sim error Error: (vsim-3464)

Error: (vsim-3464) Period of -repeat must not be less than the waveform length. This is the error message i received when i etried to run the following TCL file force -freeze CLK_DRV 0 0 , 1 { 50 ns } -r 2200; force RST_X 0; force RST_X 1 100; force CS 1 100;

BLOCK DIAGRAM OF 8085 AND FULL PDF OF 8085

BLOCK DIAGRAM OF 8085 AND FULL PDF OF 8085

constraints

can any one tell how to give constraints to a model? i need area constraints, timing constraints

VCO implementation

How do we implement VCO using vhdl?

video processing

WANTED A CODE FOR REAL TIME VIDIO PROCESSING TOREAD IMAGE ANND PROCESS IT BY 3X3 SLIDING WINDOWS AND LOW PASS FILTER

signal/function/waveform generator

please...urgent help on signal/function/waveform generator VHDL code to be implemented on Spartan3 FPGA for my final project.I want any documents and sujestions needed to implement it on fpga. Thank you for any response given to me. I am very near(some days only) to he end of the semister.please?

TCL Testbench Tutorial for Model Sim

Are there any good tutorials, pdf or documents where i can get deep knowledge in TCL scripting....????

about lut's?

why we are using LUT in FPGA? what is the advantage ? i want the complete info regarding LUT's? Plz do the needful

Oscillator for FPGA programmer

I'm developing a FPGA programmer using LFXP6C-5TN144C as core. I'm stuck with the designing of oscillatory circuit for the same. I'm stuck with the development of 24MHz circuit at 3.3v. kindly inform me were could i get this type of crystal oscillator. I have checked onto many sites like fox electronics, electronics-manufacturers....etc.but haven't found the correct one. kindly post the reply as soon as possible, so that i can fasten my work. pls, anyone who knows a solution for this problem kindly post ur views and suggestions....

about RTC

i need assembly program for my hardware; RTC ds1307, controller AT89s51, and wanna to display with 7 segment (digital clock). i wanna send (transmit) to 6 slave, and use serial communication with RS 485 to transmitting it. please give me solutions to solve it. thanks

basics of stick diagram and layout design

hi,i am a b.tech student a new vlsi learner i want to know abt stick diagram and layout design

DES encryption decryption

please send me DES encryption and decryption source code in vhdl which could run on xilinx2 simulator. I shall be grateful if u could post the code as early as possible.

USING RAM VHDL code

can anyone explain how the RAM work in vhdl code and I want 256-byte ram and how can I fill it from 0 to 255

USING RAM VHDL code

can anyone explain how the RAM work in vhdl code and I want 256-byte ram and how can I fill it from 0 to 255

vlsibank

final year projects rquired topics all from where it is always dilemma for final year students