: BZ-FAD

need vhdl code for BZ-FAD architecture.......or hot block ring counter dat was used in it...

Depth to Address width in verilog

I am reading this topic "verilog code for RAM and FIFO" in which address width of the address bus is given as - parameter ADDR_BUS_WD = 1>>DEPTH; //Address bus width My question is, why is this supposed to work? The reason I ask is because it is not working for me in Aldec's Riviera Pro tool.

Need ADC for DAQ system

am making a PC controlled data acquisition system in which i've used ADC0808 whose conversion time is 100microseconds. I want to replace it by another one having less conversion time.

Verilog code for RAM

(1) I am trying to design a 128bytes RAM similar to tht of 8051 using verilog... plz

clock division

need code for clock division in VHDL

importance of delays

What is the importance of delays in digital circuits(combinational and sequential),and what we actually mean by recovery and removal times? what is the consequence if these conditions (recovery and removal times)are not met for a circuit?

16 bit multi-operand Comparator

send me or guide for a synthesizable vhdl code for a 16 bit multi-operand comparator.