analog integrated circuits

can anyone pls explain me wats the exact need for going to analog integrated circuits? Advantage of analog integrated circuit over the digital one?

sl 100

i want to know about sl 100, it's working and application in circuit.

Phase Shift

Can anyone pl explain me how is there no phase shift in oscillator but there in amplifier.....also significance of phase shift

edge trigger Master slave

I want to konw if +ve edge triggering possible in master slave and also Is edge triggerin possible in JK flip flop

4-bit counter code in VHDL.

Have to do a 4-bit counter code in VHDL. It hads a 4 line input (A) a 10Hz CLK input a load input which is asynchronous a UP/Down (Down is Not down) and is synchronous a Reset input which is asynchronous a 2 line setect input line (x) a 2 line setect input line (y) a 4 line output (count) a one line output called (xeq Y) Does anyone know the code

dumping the vhdl code into 2 vertex II-pro kits

I am using two vertex II pro kits.I need to dump some modules into one fpga and some other into another fpga,can you tell me how to dump the code into two fpgas.

VHDL-AMS - hAMSter

I am working in hAMSter, A VHDL AMS tool. I would like to know , whether I will be able to represent a random signal, whose data I have, as a SIGNAL to be processed in a hAMSter program. The hAMSter program is developed and it is working, only thing is I should send my random data from a dat file in to the hAMSter program by some file I/o process as a "SIGNAL" or some entity. Is it possible.

Reading Files in Verilog

Can anyone help me like how it should be done? I need to Read R G B values of each pixel from 3 separate file and Write the corresponding Y U V files separately.

Solutions of Rabaey

I need solutions to Digital Integrated Ckts, Jan rabey.

counter frequency vhdl code.

need the code for counter frequency coding in vhdl.

E123 MUX / DEMUX Transceiver IP Core

please frd me to verilog code( which can be synthesized ) or block diagram or any details regarding the below mentioned.
The E123MUX is a VLSI core that provides the E13 functions needed to multiplex and demultiplex 16 independent E1 signals to and from an E3 signal that conforms to the ITU-T G.751 Recommendation. The E1 and E3 signal an interface is NRZ only. The E123MUX can also be configured to operate as an E12 or E23 multiplexer and demultiplexer. Sixteen E1 signals can be multiplexed and demultiplexed to and from four E2 signals that conform to the ITU-T G.742 Recommendation. Alternatively, four E2 signals can be multiplexed and demultiplexed to and from one E3 signal. The E2 signal interfaces are also NRZ only. Any 4 lines of 16 E1s can be multiplexed in one E2.The E123MUX uses memory locations for setting control bits and reporting status information. Microprocessor 8-bit bus provides the access of memory locations of E123MUX/DEMUX.
Feature Summary: E1 (2048 kbit/s) multiplexer/demultiplexer for ITU-T Recommendations: G.742 (8448 kbit/s E2 frame format) G.751 (34368 kbit/s E3 frame format) Multiplexer/demultiplexer converts: 16 E1s to/from 1 E3 (E13 skip mux), or 16 E1s to/from 4 E2s, or 4 E2s to/from 1 E3 (E12/E23 split mux) Select any 4 E1s to make one E2 through microprocessor interface Generates and detects E2 and E3 alarms Microprocessor input/output 8-bit bus provides split mode Intel interface

Use clock skew to increase sys. freq?

Is it possible to use clock skew (negative/positive) to actually increase the performance of the system, rather than simply having zero clock skew?

cmos comparator

want to design comparator using a charge-storage amplifier which fabricated using a 0.8μm standard logic CMOS technology,pl. give me spice model parameters.

verilog code for 5 bit sequence detector

Wanted verilog code for the sequence 11010

how to gve delay to rotate stepper motor

..plz can any body suggest me to how modify it work succesfully entity step3 is Port (clk : in STD_LOGIC; dout : out STD_LOGIC_VECTOR (3 downto 0)); end step3; architecture Behavioral of step3 is signal count:std_logic_vector(15 downto 0):=x"0000"; constant dl:time:=3 ms; begin process(clk) begin if(rising_edge(clk))then count<=count+1; dout<="1010"after dl; dout<="1001"after dl; dout<="0101"after dl; dout<="0110"after dl; if(count>x"B71B0")then count<=x"0000"; end if; end if; end process; end Behavioral;

SOC verification

have a simple SOC which contains processor , DMA and some IP peripherals. Could you please tell me how the verification flow(trigger IP)in soc level.

distance between drain and source of cmos

why do not we reduce the distance between drain and source of a cmos transistor while in the stage of fabrication it self for better multimedia appilications??? is there any limitations

vhdl code for shift register 7495

What is vhdl code for 4 bit counter 7493,shift register 7495..

vertexII

vertexII is not available,if i will implement in spartan3 is there any major diff. in the result

can we use signal in case statement

can we use signal in case statenment ,if yes how it would be synthesized..

IC 7495

please any one let me know the operation and vhdl code for ic 7495 (universal shift register)?

procedure sttements

Let me know how 2 use procedure statements with simple example?

vertexII

leonardo spectrum download

can anyone tell me from where i can download leonardo spectrum???

CODIFICADOR QPSK

needed vhdlcode for condificador qpsk

program relocation

plz send me complete notes on the PROGRAM RELOCATION FOR INTEL 8086 MICROPROCESSOR.

CMOS over BJT's

What are the advantages of using CMOS instead 0f BJTs for realizing digital circuits?

Blocking & Non Blocking

when I code Flip-Flop or Shift Registers. The data latches on the flip-flop on the next edge of the clock but not on the desired clock edge . Why does this happen . I even tried different combinations with blocking and non-blocking statements "= ,<=" The results are the same .

how to determine gate length from technology file

My question is how to determine the gate length from the interconnect technology file (ITF). For ex. the technology file I have is CONDUCTOR IPOLY_FINAL { THICKNESS=0.070 WMIN=0.045 SMIN=0.115 RPSQ=10.0 CRT1=0.0027 } From this how do you know the gate length and which process node it is.

verilog hdl

verilog hdl codes for 4-bitadders,subtractors,counters,JK-flipflop,T-flipflop

Why Microprocessor is called so

Why microprocessor is called microprocessor & why not only processor ?

VHDL FOR ADC?

CAN ANYONE HELP ME SENDING THE VHDL CODE FOR ADC0809 FPGA INTERFACE

adder

how many multiplexers are required to design a full adder

polymer

1) i wish to know that Polyphinylene vinylene is optically transperant or not? 2)solvents that can dissole PPV

verilog code 4 low power shift-and-add multiplier

needed verilog code 4 low power shift-and-add multiplier

Certifications in VLSI stream

let me know what are the certifications available for a VLSI engineer either in digital or analog stream?

RS Decoder

Can anyone send me the VHDL code for Reed Solomon Decoder(15,11).

sine wave o/p of given frequency using DAC

want to generate the sine wave of certain frequency using DAC,verilog code too needed

opcodes

needed complete opcode list for intel 8086 microprocessor.. can anyone help me out please..?

4bit risc processor

need code for 4bit risc processor

BLUE EYES TECH.

WANT TO GIVE A PRESENTATION ON BLUE EYES TECHNOLOGY. PLEASE SEND ALL INFORMATION ABOUT IT...

Active Devices

What is Active device?explain, is transistor active device or not?

logic family

Lowest noise margin in which logic family is?? a) TTL b) CMOS c) biCMOS d) all have same

how to use rocketIO in vertex-5 to invert serial t

I need to use Rocket IO(GTX) in vertex 5 to convert high speed serial data to parallel. I read ug198,ug024,ug204 of xilinx, i just want a simple code and simulation that shows serial data come and change to parallel.