Constarint to the synthesizer

There may arise a situation when tne synthesizer is allowed to selcect either a multiplexer or an and-or gate. How to keep a multiplexer constraint to the synthesizer?

leakage power in submicron technology

help me to find the leakage power of a digital NAND gate in 90nm and 65 nm technology with a HSPICE program .kindly provide the model files for the MOSFETS.Let me know the threshold voltages ,length ,width of nmos and pmos in the 90nm & 65 nm technologies.

RICS processor

1. what is the factor that depends the clock frequency of a RISC processor?
2. how to increase the speed of aRISC processor?

spi slave

want to implement an spi slave block in VHDL and I have the following question:
Do I have to use the CSn (chip select signal) as an asynchronous reset of the SPI slave block?
I don't want to use any additional master clock in order to sample the SPI signals, but I want to use the SCK to clock my flops. So I want to reset the internal FSM every time the CSn is going high.

Is this a good way to implement it?

verilog code

please provide me the verilog code for Path selector in Dual node interconnected SONET/SDH Ring for BLSR.

Number of Process Vs Simulation Time with VHDL

Does more number of processes in a vhdl design file have any effect on simulation time with Modelsim?

zero padding

i m designing an OFDM transceiver in xilinix system generator. i took data and modulated the data using QPSK. then before giving my data to IFFT i need to do its zero padding. my incoming data is at the rate of 800 samples per sec. i want to take 1st 400 samples and store them. i tried to use RAM of depth 400(i dont know i m right or wrong), then next 400 samples in another RAM. and now i want to add 224 zeros in between these two data samples of 400. My data rate has been increases from 800 samples/sec to 1024. How can i store this higher sample rate. and how can i implement my problem in system generator. can i use FIFO any where.