want to implement an spi slave block in VHDL and I have the following question:
Do I have to use the CSn (chip select signal) as an asynchronous reset of the SPI slave block?
I don't want to use any additional master clock in order to sample the SPI signals, but I want to use the SCK to clock my flops. So I want to reset the internal FSM every time the CSn is going high.
Is this a good way to implement it?
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