Voltage Source & capacitor, Voltage source & Diode

what will be the Output voltage when a Capacitor is connected to a voltage source in series. The circuit is not closed Figure ----------. Vin vout1 ____________. Similarly instead of a capacitor if a diode is connected what will be the output ------ -> ----. Vin vout2 ______________. ------ <- ----. Vin vout3 ->,<- are diodes ______________.

Embedded Systems

in future the growth and offers in embedded..

vhdl for nco(DDS)

urgently required a dds signal genarator vhdl description to implement it on spartan3 xilinx fpga using xilinx 8.2.I want all the files needed to implement it.And How can I use lpm components(or instead of them) like lpm rom,lpm ff,lpm add sub in xilinx ise8.2?

VHDL code for CIC Decimation

I need a general code for vhdl cic decimator for factor 5. My Fs is 400Mhz and IF is 5Mhz.

cts spec generation

what are the mandatory inputs needed to generate clock tree specification file with encounter and how to generate clock tree spec file for perticular design

need guidence to give connstraints

need to learn to give constraints to a verilog model using xylinx sparten 2 xst200 pq208

need guidence to give connstraints

need to learn to give constraints to a verilog model using xylinx sparten 2 xst200 pq208