How to resimulate a verilog-A simulation?

I have simulated a verilog-A netlist using spectre.
I have the savetime file (*.srf) at 55us.
I want to re-simulate design from 55us to 100us.
While doing so, the verilog A models are giving wrong result.

Can anybody tell me how to re-simulate the design.

guidance program

iwant program in "verilog" to giude amissile ,IF the input of target are none {Module Guidance(trgt_distination,trgt_velocity,angle).
THE MISSLE IS GOING ON{x,y}axis (that mean we used the Laws of linear motion )


(by using fpga )

how to implement vhdl coding on fpga

i am doing booth encoded wallace tree multiplier(32 bit) using VHDL/VERILOG .
but i don't know how to implement vhdl code on fpga board .
i am using SPARTAN 3E KIT (FPGA BOARD).

please send me the steps how to run the coding on fpga board FOR 32 BIT VHDL CODE.

Keypad Scanner & LCD

I am trying to program the FPGA such that it takes inputs from HEX Keypad & show the output on LCD. Ex. pressing 4 5 6 9 8 on Keypad should display 45698 on the lcd.
suggest me the logic or some sample codes in VHDl to guide me through..

Matrix Mutliplication

i am planning to design the matrix multiplication,IF any one have the good material for this plz provide me.

2x1 mux using half adders

I need a circuit for 2x1 mux using half adders

Are real nos in VHDL synthesizable???

how to find the average and variance of 25 complex numbers in VHDL.the complex numbers are generated using matlab.I have 2000 complex nos of which i have to find average and variance taking 25 complex nos at a time.

In VHDL, are real nos not synthesisable??if so how should i convert complex no to STD_LOGIC_VECTOR..
pls help me in this regard...,